97 Open source projects that are alternatives of or similar to YatCPU-docs

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Quasar 2.0: Chisel equivalent of SweRV-EL2

Yet another toy CPU.

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

Embedded Rust's Peripheral Access Crate for BL602 microcontrollers

Simple RISC-V 3-stage Pipeline in Chisel

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

RISC-V RV32I[MAC] emulator with ELF support

Nuclei RISC-V Software Development Kit

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位

A RISC-V simulator

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

The Gee (寂) Operating System, written in YuLang.

A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python

F# RISC-V Instruction Set formal specification

An unofficial reference sheet for RISC-V.

RISC-V SystemC-TLM simulator

UNIX-like operating system written in C and C++

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

riscv资料、论文等

Simple risc-v emulator, able to run linux, written in C.

Lectures for the Agile Hardware Design course in Jupyter Notebooks

FPGA-based RISC-V CPU+SoC.

RISC-V Instruction Set Metadata

Sedna - a pure Java RISC-V emulator.

Freedom U Software Development Kit (FUSDK)

MDEPX — A BSD-style RTOS

Riscy Processors - Open-Sourced RISC-V Processors

Yet Another RISC-V Implementation

Shakti: development platform for PlatformIO

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

CKB's vm, based on open source RISC-V ISA

异步内核就像风一样快！

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

SoC based on VexRiscv and ICE40 UP5K

Tests for example Rocket Custom Coprocessors

Rocket Chip Generator

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

Reference implementation for the book "Writing a RISC-V Emulator in Rust".

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

Rust version of THU uCore OS. Linux compatible.

Jonesforth RISC-V port.

OpenEmbedded/Yocto layer for RISC-V Architecture

FIPS and higher-level algorithm tests for RISC-V Crypto Extension

homebrew (macOS) packages for RISC-V toolchain

Ultra light weight small device firmware. Well architected to support MMU, SMP, low power idle. Can be run on various CPU architectures.

SweRV EL2 Core

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

bl602 serial flasher

FPGA 101 - Workshop materials

pulp_soc is the core building component of PULP based SoCs

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

RISCV SoftCPU Contest 2018

ARV: Asynchronous RISC-V Go High-level Functional Model

This repo contains the artifact for our SOSP'19 paper on Serval

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!