549 Open source projects that are alternatives of or similar to K1801

谷歌工程实践

SERV - The SErial RISC-V CPU

😎 All the required resources to build your own startup

Verilog AXI components for FPGA implementation

YourView is a desktop App in MacOS based on Apple SceneKit. You may use it to view iOS App's view hierarchy 3D.

RISC-V Formal Verification Framework

🦄 Sourcerer app makes a visual profile from your GitHub and git repositories.

A curated list of delightful and free automotive engineering resources, looking for contributors ❗

CTF 工具集合

RF and Microwave Engineering Scikit

Scala based HDL

Open source JavaScript SDK for viewing high-detail, full-precision 3D BIM and AEC models in the Web browser.

High performance motor control

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

A CPU that implementing THCO-MIPS16 instruction set.

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

😎 Curated list of awesome software for numerical analysis and scientific computing

😱 Falsehoods Programmers Believe in

Transmits AM radio on computers without radio transmitting hardware.

The OpenPiton Platform

Accumulated knowledge and experience in the field of Data Engineering

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

a reverse TCP tunnel let you access target behind NAT or firewall

OpenROAD's unified application implementing an RTL-to-GDS Flow

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Various HDL (Verilog) IP Cores

Preparation links and resources for system design questions

Mesh optimization, mesh smoothing.

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Verilog PCI express components

KT-Link compatible buffer for the Bus Blaster v3

Test suite designed to check compliance with the SystemVerilog standard.

Golang Restful API Framework for Productivity

Haskell library for hardware description

An open source GPU based off of the AMD Southern Islands ISA.

A scanner similar to bufio.Scanner, but it reads and returns lines in reverse order, starting at a given position and going backward.

A curated list of references for MLOps

Collection of top articles about great software engineering practices.

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Functions that can be used to gain Reverse Shells with PowerShell

TensorBase BE is building a high performance, cloud neutral bigdata warehouse for SMEs fully in Rust.

Interactive Multiphysics Simulation for Everyone

A small, light weight, RISC CPU soft core

Invert a given color.

Gmsh for Python

This repo is for the 4618 group nember to share code.

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

Scripts to build and use docker images including GHDL

Verilog library for ASIC and FPGA designers

RHEOS - Open Source Rheology data analysis software

MIPS CPU implemented in Verilog

Automating management tasks to help managers focus on more strategic wins.

Classical Aerodynamics of potential flow using Python and Jupyter Notebooks

No description or website provided.

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Droidefense: Advance Android Malware Analysis Framework

Hardware Description Languages

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Java library for parsing and manipulating graph representations of gate-level Verilog netlists