ultraembedded / Cores
Various HDL (Verilog) IP Cores
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Various HDL (Verilog) IP Cores
Github: http://github.com/ultraembedded/cores
Cloning
This repo contains submodules, to clone them;
git clone --recursive https://github.com/ultraembedded/cores.git
Catalogue
Name | Description |
---|---|
asram16_axi4 | AXI4 -> Async SRAM (16-bit) Interface |
dbg_bridge | UART -> AXI4 Debug Bridge |
dvi_framebuffer | DVI/HDMI framebuffer with AXI-4 bus master |
ftdi_async_bridge | FTDI Asynchronous FIFO Interface (Wishbone) |
ftdi_bridge | FTDI Asynchronous/Synchronous FIFO Interface (AXI-4) |
ft60x_axi | FTDI FT601 USB3.0 to high-performance AXI4 bus master |
i2s | I2S Master |
irq_ctrl | Simple Linux support interrupt controller |
sdram | Simple SDRAM Controller (Wishbone) |
sdram_axi4 | Simple SDRAM Controller (AXI-4) |
spdif | SPDIF Transmitter |
spiflash | SPI-Flash XIP Interface |
spilite_axi4l | SPI-Lite SPI Master Interface |
uart | UART |
ulpi_wrapper | ULPI Link Wrapper |
usb_bridge | USB -> AXI4-Lite Debug Bridge |
usb_cdc | USB CDC Device |
usb_device | USB Peripheral Interface |
usb_fs_phy | USB Full Speed PHY |
usb_host | USB 1.1 Host Controller |
usb_sniffer | USB Sniffer |
usb_serial | USB to UART |
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