All Git Users → syntacore

3 open source projects by syntacore

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SCR1 is a high-quality open-source RISC-V MCU core in Verilog

✭ 393

verilog ip core risc-v rtl riscv

2. fpga-sdk-prj

FPGA-based SDK projects for SCRx cores

✭ 15

Verilog tcl SystemVerilog

open-source SDKs for the SCR1 core

✭ 61

c Makefile assembly

1-3 of 3 user projects