VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
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Mutual labels: fpga, riscv
Fpga101 WorkshopFPGA 101 - Workshop materials
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F32cA 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
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Neorv32A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
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FuxiFuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
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Darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
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Cva6The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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Cores Swerv El2SweRV EL2 Core
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Ustc RvsocFPGA-based RISC-V CPU+SoC.
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yarviYet Another RISC-V Implementation
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kianRiscVKianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
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KyogenRVThe Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
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T13xAn Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
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pygearsHW Design: A Functional Approach
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JSON-for-VHDLA JSON library implemented in VHDL.
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shapool-coreFPGA core for SHA256d mining targeting Lattice iCE40 devices.
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QNICE-FPGAQNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
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spectorSpector: An OpenCL FPGA Benchmark Suite
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usbcorevA full-speed device-side USB peripheral core written in Verilog.
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