396 Open source projects that are alternatives of or similar to riscv-contest-2018

SweRV EH1 core

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FPGA-based RISC-V CPU+SoC.

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The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

RISC-V RV32I[MAC] emulator with ELF support

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An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

A JSON library implemented in VHDL.

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Generic FPGA SDRAM controller, originally made for AS4C4M16SA

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Antmicro's fast, vendor-neutral DMA IP in Chisel

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FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

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Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

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