verilator / Verilator
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Welcome to Verilator
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Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.
- Accepts synthesizable Verilog or SystemVerilog
- Performs lint code-quality checks
- Compiles into multithreaded C++, or SystemC
- Creates XML to front-end your own tools
- |Logo|
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Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.
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- |verilator multithreaded performance bg min|
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Fast
- Outperforms many commercial simulators
- Single- and multi-threaded output models
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Widely Used
- Wide industry and academic deployment
- Out-of-the-box support from Arm, and RISC-V vendor IP
- |verilator usage 400x200 min|
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Widely Used
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- |verilator community 400x125 min|
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Community Driven & Openly Licensed
- Guided by the
CHIPS Alliance
_ andLinux Foundation
_ - Open, and free as in both speech and beer
- More simulation for your verification budget
- Guided by the
-
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Commercial Support Available
- Commercial support contracts
- Design support contracts
- Enhancement contracts
- |verilator support 400x125 min|
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Commercial Support Available
What Verilator Does
Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp and .h files, the "Verilated" code.
The user writes a little C++/SystemC wrapper file, which instantiates the "Verilated" model of the user's top level module. These C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
Verilator may not be the best choice if you are expecting a full featured
replacement for NC-Verilog, VCS or another commercial Verilog simulator, or
if you are looking for a behavioral Verilog simulator e.g. for a quick
class project (we recommend Icarus Verilog
_ for this.) However, if you
are looking for a path to migrate SystemVerilog to C++ or SystemC, or your
team is comfortable writing just a touch of C++ code, Verilator is the tool
for you.
Performance
Verilator does not simply convert Verilog HDL to C++ or SystemC. Rather,
Verilator compiles your code into a much faster optimized and optionally
thread-partitioned model, which is in turn wrapped inside a C++/SystemC
module. The results are a compiled Verilog model that executes even on a
single-thread over 10x faster than standalone SystemC, and on a single
thread is about 100 times faster than interpreted Verilog simulators such
as Icarus Verilog
_. Another 2-10x speedup might be gained from
multithreading (yielding 200-1000x total over interpreted simulators).
Verilator has typically similar or better performance versus the closed-source Verilog simulators (Carbon Design Systems Carbonator, Modelsim, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on computes rather than licenses. Thus Verilator gives you the best cycles/dollar.
For more information on how Verilator stacks up to some of the other
closed-sourced and open-sourced Verilog simulators, see the Verilog Simulator Benchmarks <https://www.veripool.org/verilog_sim_benchmarks.html>
. (If you
benchmark Verilator, please see the notes in the Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>
, and also if possible post on
the forums the results; there may be additional tweaks possible.)
Installation & Documentation
For more information:
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Verilator installation and package directory structure <https://verilator.org/install>
_ -
Verilator manual (HTML) <https://verilator.org/verilator_doc.html>
, orVerilator manual (PDF) <https://verilator.org/verilator_doc.pdf>
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Subscribe to verilator announcements <https://github.com/verilator/verilator-announce>
_ -
Verilator forum <https://verilator.org/forum>
_ -
Verilator issues <https://verilator.org/issues>
_
Support
Verilator is a community project, guided by the CHIPS Alliance
_ under the
Linux Foundation
_.
We appreciate and welcome your contributions in whatever form; please see
Contributing to Verilator <https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst>
.
Thanks to our Contributors and Sponsors <https://verilator.org/verilator_doc.html#CONTRIBUTORS>
.
Verilator also supports and encourages commercial support models and
organizations; please see Verilator Commercial Support <https://verilator.org/verilator_commercial_support>
_.
Related Projects
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GTKwave <http://gtkwave.sourceforge.net/>
_ - Waveform viewer for Verilator traces. -
Icarus Verilog
_ - Icarus is a full featured interpreted Verilog simulator. If Verilator does not support your needs, perhaps Icarus may.
Open License
Verilator is Copyright 2003-2021 by Wilson Snyder. (Report bugs to
Verilator Issues <https://verilator.org/issues>
_.)
Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. See the documentation for more details.
.. _CHIPS Alliance: https://chipsalliance.org .. _Icarus Verilog: http://iverilog.icarus.com .. _Linux Foundation: https://www.linuxfoundation.org .. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png .. |verilator multithreaded performance bg min| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png .. |verilator usage 400x200 min| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png .. |verilator community 400x125 min| image:: https://www.veripool.org/img/verilator_community_400x125-min.png .. |verilator support 400x125 min| image:: https://www.veripool.org/img/verilator_support_400x125-min.png