VerilogRepository for basic (and not so basic) Verilog blocks with high re-use potential
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Icezum🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board
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Scr1SCR1 is a high-quality open-source RISC-V MCU core in Verilog
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KgtBNF wrangling and railroad diagrams
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Fake-SDcardImitate SDcard using FPGAs.
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Sd2snesSD card based multi-purpose cartridge for the SNES
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DevitoCode generation framework for automated finite difference computation
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BinaryenCompiler infrastructure and toolchain library for WebAssembly
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CoresVarious HDL (Verilog) IP Cores
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Apio🌱 Open source ecosystem for open FPGA boards
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Mor1kxmor1kx - an OpenRISC 1000 processor IP core
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cs-resourcesCurated Computer Science and Programming Resource Guide
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Open Fpga Verilog TutorialLearn how to design digital systems and synthesize them into an FPGA using only opensource tools
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Beagle sdr gpsKiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
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UhdThe USRP™ Hardware Driver Repository
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OpenlaneOpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
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CascadeA Just-In-Time Compiler for Verilog from VMware Research
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OpenpitonThe OpenPiton Platform
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OhVerilog library for ASIC and FPGA designers
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OpenroadOpenROAD's unified application implementing an RTL-to-GDS Flow
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Awesome HdlHardware Description Languages
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Verilog PcieVerilog PCI express components
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real-world-idrisMalfunction backend for Idris with a FFI to OCaml
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Verilog AxiVerilog AXI components for FPGA implementation
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3bc-langLow level language, tiny virtual machine that works on computers and microcontrollers. (Friendly Punched cards)
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RiffaThe RIFFA development repository
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Platformio CorePlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!
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ReduceronFPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.
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Simd VisualiserA tool to graphically visualize SIMD code
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HellscapeGIMPLE obfuscator for C, C++, Go, ... all supported GCC targets and front-ends that use GIMPLE.
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LeflowEnabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
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VerilogboyA Pi emulating a GameBoy sounds cheap. What about an FPGA?
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Ucr Eecs168 LabThe lab schedules for EECS168 at UC Riverside
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Mips CpuMIPS CPU implemented in Verilog
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NetfpgaNetFPGA 1G infrastructure and gateware
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ZipcpuA small, light weight, RISC CPU soft core
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RiscvRISC-V CPU Core (RV32IM)
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PrjtrellisDocumenting the Lattice ECP5 bit-stream format.
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LibfsmDFA regular expression library & friends
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EdalizeAn abstraction library for interfacing EDA tools
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MicrowattA tiny Open POWER ISA softcore written in VHDL 2008
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CompilingtheoryMy course design for compiler theory (Visualization).
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WgtccA small C11 compiler
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sv-testsTest suite designed to check compliance with the SystemVerilog standard.
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ServSERV - The SErial RISC-V CPU
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blarneyHaskell library for hardware description
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Platformio Atom IdePlatformIO IDE for Atom: The next generation integrated development environment for IoT
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Como Lang Ngcomo-lang-ng is now ana-lang, located at https://github.com/analang/ana
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MiaowAn open source GPU based off of the AMD Southern Islands ISA.
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SdcIntel® Scalable Dataframe Compiler for Pandas*
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CorundumOpen source, high performance, FPGA-based NIC
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Micro MittenYou might not need your garbage collector
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Riscv FormalRISC-V Formal Verification Framework
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