557 Open source projects that are alternatives of or similar to oscimpDigital

🔊 Ultrasound imaging with RTL-SDR

This repo is for ECE44x (Fall2015-Spring2016)

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SpinalHDL - Cryptography libraries

FPGA based USB 2.0 high speed audio interface featuring multiple optical ADAT inputs and outputs

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Chisel components for FPGA projects

SystemOT, yet another home brew cpu.

unireact - quickly bootstrap your universal react-app

Dockerfile with Vivado for CI

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Schematic symbol libraries for FPGAs & microcontrollers.

An open-source VHDL library for FPGA design.

MOS6581 SID chip emulator in SystemVerilog

VT220-compatible console on Cyclone IV EP4CE55F23I7

Linux Driver for USB WiFi Adapters that are based on the RTL8814AU Chipset

Soapy SDR plugin for SDRPlay APIv3

nrsc5 (HD FM) radio player

Low-cost ECP5 FPGA development board

Unofficial Yosys WebAssembly packages

Mostly AVR compatible FPGA soft-core

Snapcast OS

High-speed LaserDisc RF sampler

This repository contains iCEBreaker examples for Amaranth HDL.

GNURadio blocks to remove that IQ DC spike just like some software and drivers do! Three techniques available: auto, auto-tune to dc offset, and manual.

PandA-bambu public repository

DMA source and sink blocks for Xilinx Zynq FPGAs

Sphinx Extension which generates various types of diagrams from Verilog code.

Implementation of PCI drivers, kprobe, sysfs, devfs, sensor driver, miscdevices, synchronization

GSM Scanner, RTL-SDR, StingWatch, Meteor

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

FPGA-based LPC bus sniffing tool for Lattice iCEstick Evaluation Kit

RFSec tools

IceChips is a library of all common discrete logic devices in Verilog

WSPR daemon for RTL receivers

A Vivado HLS Command Line Helper Tool

SneakySnake🐍 is the first and the only pre-alignment filtering algorithm that works efficiently and fast on modern CPU, FPGA, and GPU architectures. It greatly (by more than two orders of magnitude) expedites sequence alignment calculation for both short and long reads. Described in the Bioinformatics (2020) by Alser et al. https://arxiv.org/abs…

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Simulation of the classic Pacman arcade game on a PanoLogic thin client.

HD Radio SDR Receiver

Soapy SDR plugin for Audio devices

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

vdl mode 2 SDR decoder

Virtio implementation in SystemVerilog

Networked DFing software that can handle multiple DOA receivers.

ROS 2 Hardware Acceleration Working Group community governance model & list of projects

RISC-V Cores, SoC platforms and SoCs

This package provides GNUradio OOT modules and grc flowgraphs that fascilates Radio Astronomy Observations with software defined radio devices.

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Accelerated Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators

3D visualization of air traffic through RTL-SDR (dump1090) and MATLAB

No-MMU Linux capable RISC-V SoC designed to be useful.

FPGA Assembly (FASM) Parser and Generator

Install Intel FPGA 'Quartus Prime' software on remote servers

主流国际中文电台短波接收频率

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Guide to aircraft tracking using ADS-B reception with SDR & docker containers. Published on GitBook.

Header only C++14 library containing various digital signal processing utilities.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

👁️ An authorial set of fundamental Python recipes on Computer Vision and Digital Image Processing.