SpinalDevDocker Development Environment for SpinalHDL
Stars: ✭ 17 (-52.78%)
Mutual labels: fpga, vhdl, rtl, verilog, spinalhdl
EasyEncryptionNo description or website provided.
Stars: ✭ 16 (-55.56%)
Mutual labels: aes, md5, sha, des
hwtVHDL/Verilog/SystemC code generator, simulator API written in python/c++
Stars: ✭ 145 (+302.78%)
Mutual labels: fpga, vhdl, rtl, verilog
webcryptoA WebCrypto Polyfill for NodeJS
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Mutual labels: aes, sha, hmac, des
SpinalhdlScala based HDL
Stars: ✭ 696 (+1833.33%)
Mutual labels: fpga, vhdl, rtl, verilog
J1scA reimplementation of a tiny stack CPU
Stars: ✭ 64 (+77.78%)
Mutual labels: fpga, vhdl, verilog
Ustc RvsocFPGA-based RISC-V CPU+SoC.
Stars: ✭ 77 (+113.89%)
Mutual labels: fpga, rtl, verilog
cnn openA hardware implementation of CNN, written by Verilog and synthesized on FPGA
Stars: ✭ 157 (+336.11%)
Mutual labels: fpga, rtl, verilog
virtioVirtio implementation in SystemVerilog
Stars: ✭ 38 (+5.56%)
Mutual labels: fpga, rtl, verilog
Image ProcessingImage Processing Toolbox in Verilog using Basys3 FPGA
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Mutual labels: fpga, vhdl, verilog
LogicCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Stars: ✭ 149 (+313.89%)
Mutual labels: fpga, rtl, verilog
Fpga readingsRecipe for FPGA cooking
Stars: ✭ 164 (+355.56%)
Mutual labels: fpga, rtl, verilog
RggenCode generation tool for configuration and status registers
Stars: ✭ 54 (+50%)
Mutual labels: fpga, rtl, verilog
Darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Stars: ✭ 1,062 (+2850%)
Mutual labels: fpga, rtl, verilog
AesVerilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
Stars: ✭ 131 (+263.89%)
Mutual labels: fpga, aes, verilog
VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
Stars: ✭ 1,041 (+2791.67%)
Mutual labels: fpga, vhdl, verilog
TinytpuImplementation of a Tensor Processing Unit for embedded systems and the IoT.
Stars: ✭ 153 (+325%)
Mutual labels: fpga, vhdl, verilog
vga-clockShow the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Stars: ✭ 48 (+33.33%)
Mutual labels: fpga, rtl, verilog
vscode-terosHDLVHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Stars: ✭ 325 (+802.78%)
Mutual labels: fpga, vhdl, verilog
crypto🔐 Fastest crypto library for Deno written in pure Typescript. AES, Blowfish, CAST5, DES, 3DES, HMAC, HKDF, PBKDF2
Stars: ✭ 40 (+11.11%)
Mutual labels: aes, hmac, des