462 Open source projects that are alternatives of or similar to tree-core-cpu

💻 A very simple redis monitor based on Flask and React. 一个部署简单的 redis 监控程序，使用 Flask 和 React 完成。

riscv资料、论文等

Monitor server CPU / Memory / Process / Zombie Process / Disk size / Security Packages / Network Input / Network Output

FPGA 101 - Workshop materials

Android performance test

Acceleration package for neural networks on multi-core CPUs

Node.js in-process collectors for Instana

Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.

iOS 任务调度器，为 CPU 和内存减负（用于性能优化）

The Hybrid Task Graph Scheduler API

This is the release repository for Fan Control, a highly customizable fan controlling software for Windows.

☔️ interface for parsing, inspecting, transforming, and serializing content through syntax trees

Bistoury是去哪儿网的java应用生产问题诊断工具，提供了一站式的问题诊断方案

Native Operating System and Hardware Information

A lightweight system monitor similar to conky with html and css for themes

Visual Inertial Odometry with SLAM capabilities and 3D Mesh generation.

A markdown processor written in Go. built for fun.

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

CPU Based Rasterizer Engine

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

Schematics & code for my 74LS-based 8-bit MK1 CPU

A self-hosting and educational C compiler

Deliver empathetic experiences to your users by adapting to their capabilities

Tengine is a lite, high performance, modular inference engine for embedded device

Project Migration tools to help you migrating to IAR Embedded Workbench more efficiently.

High-resolution clock functions: monotonic, realtime, cputime.

支持CMSIS-DAP v2接口协议，支持ARM、RISCV、ESP32等目标芯片，详见Wiki及release

Freedom U Software Development Kit (FUSDK)

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

CPU Ultimate Latency Test.

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

A Python Library for Genetic Algorithm on OpenCL

⛔ DEPRECATED ⛔ HERO Software Development Kit

The Sherwood Architecture is a custom 64-Bit RISC based CPU architecture.

Documentatin for YatCPU

Pubg Mobile Emulator Gameloop Memory Hacking C++ code examples. Ex: Name, Coord, Bones, Weapons, Items, Box, Drop etc.

RISCV SoftCPU Contest 2018

RISC-V SystemC-TLM simulator

Statsy is a easy to use open source PHP tool for developers, that allows you to return various types of information about your server.

The Gee (寂) Operating System, written in YuLang.

Bash script to kill high CPU process, long running process and too much consuming memory process.

RISC-V RV32I[MAC] emulator with ELF support

A compiler, assembler, and processor.

Simple risc-v emulator, able to run linux, written in C.

Achieve peak performance on x86 CPUs and NVIDIA GPUs

Sedna - a pure Java RISC-V emulator.

Android library to display various debugging information in an overlay window

Yet Another RISC-V Implementation

⚡ Proof your app maintains 60-ish FPS by collecting data or showing it on screen with this NativeScript plugin!

异步内核就像风一样快！

32-bit Superscalar RISC-V CPU

A PDF processor written in Go.

CPU-X is a Free software that gathers information on CPU, motherboard and more

A simple RISC-V processor for use in FPGA designs.

Jest test results processor for generating a summary in HTML

Get CPU, Memory and Network informations of the running OS and its processes

ncnn android benchmark app

Python script and a PyQt5 program to monitor ram and cpu usage along with disk usage.

Version 2 of my Crazy Small CPU

Collection of links to great software development resources!