9 open source projects by openhwgroup

Instruction Set Generator initially contributed by Futurewei

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

CVA6 SDK containing RISC-V tools and Buildroot

CORE-V Family of RISC-V Cores

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

4 stage, in-order, secure RISC-V core based on the CV32E40P

Functional verification project for the CORE-V family of RISC-V cores.