Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

✭ 131

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Open Register Design Tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

✭ 126

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Skywater Pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

✭ 1,765

python shell Makefile magic eda asic pdk asic-library openroad openram skywater

Livehd

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

✭ 110

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Systemrdl Compiler

SystemRDL 2.0 language compiler front-end

✭ 95

python fpga eda asic

Cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

✭ 1,144

fpga cpu riscv asic

Rggen

Code generation tool for configuration and status registers

✭ 54

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Clash Compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

✭ 958

haskell verilog fpga vhdl asic

Embedded Neural Network

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

✭ 495

deep-learning neural-network compression fpga asic

Riscv Cores List

RISC-V Cores, SoC platforms and SoCs

✭ 471

fpga risc-v asic

Vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

✭ 438

unit-testing fpga vhdl verification asic

Dss

Digital Signature Service : creation, extension and validation of advanced electronic signatures

✭ 415

java validation signature asic

Openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

✭ 293

verilog rtl magic asic

Riscv

RISC-V CPU Core (RV32IM)

✭ 272

verilog fpga cpu verification risc-v asic

Cores

Various HDL (Verilog) IP Cores

✭ 271

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awesome-dv

Awesome ASIC design verification

✭ 76

asic verification uvm formal-verification asic-verification

qwertycoin

Qwertycoin is a decentralized peer-to-peer protocol for safe payments worldwide.

✭ 37

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VGChips

Video Game custom chips reverse-engineered from silicon

✭ 86

Verilog asic fpga reverse-engineering arcade verilog chip hdl silicon cpld repro taito decap

DFiant

DFiant: A Dataflow Hardware Descripition Language

✭ 21

scala asic fpga dataflow dataflow-programming hdl

FPGA CryptoNight V7

FPGA CryptoNight V7 Minner

✭ 21

Verilog asic fpga blockchain monero minner cryptonight-v7

PeakRDL-uvm

Generate UVM register model from compiled SystemRDL input

✭ 25

python SystemVerilog shell asic fpga eda uvm registers uvm-ral-model uvm-register-model

cdc

Repository gathering basic modules for CDC purpose

✭ 30

SystemVerilog Verilog forth asic timing fifo cdc fgpa cross-domain-crossing pulse-synchronizer

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

✭ 116

c assembly SystemVerilog python C++Makefile asic cpu vector riscv ara rvv rv64gcv

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

✭ 548