Top 10 uvm open source projects

Awesome ASIC design verification

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Generate UVM register model from compiled SystemRDL input

🐌Yet Another Simulation Architecture

AMBA AXI VIP

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

Network on Chip Implementation written in SytemVerilog

Download proccedings from DVCon

Universal Virtual Machine for Node and Browser

Functional verification project for the CORE-V family of RISC-V cores.