20 open source projects by ucb-bar

Simple RISC-V 3-stage Pipeline in Chisel

Verilog version of Z-scale (deprecated)

UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM

A Library of Chisel3 Tools for Digital Signal Processing

SoftFloat release 3

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel tutorial exercises and answers

educational microarchitectures for risc-v isa

Support for Rocket Chip on Zynq FPGAs

A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)

Fork of upstream onnxruntime focused on supporting risc-v accelerators

Berkeley's Spatial Array Generator

Template for projects using the Hwacha data-parallel accelerator

A prototype GUI for chisel-development

No description, website, or topics provided.

Z-scale Microarchitectural Implementation of RV32 ISA

RISC-V Torture Test