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Top 2 icarus-verilog open source projects

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

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Verilog SystemVerilog fpga verification verilog synthesis icarus-verilog fifo hdl verilog-hdl fifo-queue fifo-cache

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

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python SystemVerilog shell Verilog C++simulator tdd simulation foss verilog testcase tdd-utilities mit-license icarus-verilog gtkwave verification-methodologies vcd verilator svut

1-2 of 2 icarus-verilog projects