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Top 23 hdl open source projects

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

✭ 148

SystemVerilog python javascript CSS HTML Makefile rtl verilog hdl compliance-testing symbiflow

Speech256

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

✭ 51

Verilog python fpga speech synthesizer verilog hdl retrochallenge

VGChips

Video Game custom chips reverse-engineered from silicon

✭ 86

Verilog asic fpga reverse-engineering arcade verilog chip hdl silicon cpld repro taito decap

DFiant

DFiant: A Dataflow Hardware Descripition Language

✭ 21

scala asic fpga dataflow dataflow-programming hdl

act

ACT hardware description language and core tools.

pygears

HW Design: A Functional Approach

✭ 122

python Verilog Jinja SystemVerilog c shell design functional simulator asic fpga hardware hdl

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

✭ 20

python Verilog Makefile interface bus vhdl verilog hdl testbench cocotb

arv

ARV: Asynchronous RISC-V Go High-level Functional Model

✭ 18

go c python Makefile assembly hardware asynchronous processor riscv hdl risc-v riscv32 qdi

hdelk

Web-based HDL diagramming tool

✭ 51

javascript HTML browser fpga graphs edges diagrams nodes hdl elkjs hdelk

symbolator

HDL symbol generator

✭ 123

python vhdl verilog symbol hdl

cpu11

Revengineered ancient PDP-11 CPUs, originals and clones

✭ 120

Verilog Stata python c Batchfile AL engineering verilog reverse retrocomputing hdl pdp-11 cpucore

yavhdl

Yet Another VHDL tool

✭ 29

Yacc rust C++Lex VHDL python vhdl eda hdl

vboard

Virtual development board for HDL design

✭ 32

VHDL python c Makefile shell vhdl verilog hdl ghdl cosim vpi verilator fli vhpidirect

async fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

✭ 117

Verilog SystemVerilog fpga verification verilog synthesis icarus-verilog fifo hdl verilog-hdl fifo-queue fifo-cache

migen-axi

AXI support for Migen/MiSoC

✭ 21

python hdl misoc migen zynq-7000

icebreaker-amaranth-examples

This repository contains iCEBreaker examples for Amaranth HDL.

✭ 26

python fpga hardware electronics hdl gateware

sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

✭ 37

python Makefile Verilog documentation fpga sphinx documentation-tool rtl verilog diagrams hdl yosys sphinx-extension symbiflow

virtio

Virtio implementation in SystemVerilog

✭ 38

SystemVerilog CMake python Vim Script cmake fpga model rtl verilog xilinx vivado systemc hdl virtio verilator quartus

hdl-tools

Facilitates building open source tools for working with hardware description languages (HDLs)

✭ 56

perl tcl Makefile shell rtl verilog gtkwave hdl verilator

gateware-ts

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

✭ 83

typescript javascript fpga hardware simulation verilog hdl gateware

Technocrats-HacktoberFest

This Repository invites freelancer friendly neighbourhood developers to contribute to open source .

shdl6800

shdl6800: A 6800 processor written in SpinalHDL

✭ 22

scala Makefile fpga hdl spinalhdl 6800 nmigen

xeda

Cross EDA Abstraction and Automation

✭ 25

python tcl automation fpga hardware simulation vhdl eda verilog synthesis hdl

1-23 of 23 hdl projects