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Top 13 verilator open source projects

CMod-S6 SoC

✭ 30

Verilog c C++assembly Makefile perl objective c fpga fpga-soc wishbone verilator zipcpu wishbone-bus

Quasar 2.0: Chisel equivalent of SweRV-EL2

✭ 19

scala SystemVerilog perl c Verilog C++processor chisel riscv rtl chisel3 open-source-hardware verilator asic-verification axi4 ahb-lite asic-design swerv swerv-el2

A collection of phase locked loop (PLL) related projects

✭ 55

Verilog C++matlab Makefile shell fpga gplv3 verilog verilator pll

Wishbone controlled I2C controllers

✭ 25

Verilog C++Lex Makefile c shell assembly fpga i2c gplv3 verilog verilator i2c-slave wishbone-bus i2c-master

A configurable C++ generator of pipelined Verilog FFT cores

✭ 147

C++Verilog Makefile c fpga gplv3 verilog fft verilog-components verilator

An Open Source configuration of the Arty platform

✭ 93

Verilog C++Coq c Makefile shell fpga fpga-soc wishbone verilator arty zipcpu wishbone-bus

rules verilator

Bazel build rules for Verilator

✭ 14

Starlark bazel bazel-rules verilog verilator

Virtual development board for HDL design

✭ 32

VHDL python c Makefile shell vhdl verilog hdl ghdl cosim vpi verilator fli vhpidirect

Virtio implementation in SystemVerilog

✭ 38

SystemVerilog CMake python Vim Script cmake fpga model rtl verilog xilinx vivado systemc hdl virtio verilator quartus

Facilitates building open source tools for working with hardware description languages (HDLs)

✭ 56

perl tcl Makefile shell rtl verilog gtkwave hdl verilator

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

✭ 22

scala shell Makefile python C++Verilog cpu processor chisel riscv rtl rt-thread verilator softcore

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

✭ 48

python SystemVerilog shell Verilog C++simulator tdd simulation foss verilog testcase tdd-utilities mit-license icarus-verilog gtkwave verification-methodologies vcd verilator svut

A collection of debugging busses developed and presented at zipcpu.com

✭ 24

Verilog C++Makefile c shell verilog debugging-tools wishbone fgpa verilator wishbone-bus

1-13 of 13 verilator projects