Speech256An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
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Darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
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OpenpitonThe OpenPiton Platform
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1bitSDRMinimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
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VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
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VGChipsVideo Game custom chips reverse-engineered from silicon
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Jt gngCAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.
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CoresVarious HDL (Verilog) IP Cores
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ZipcpuA small, light weight, RISC CPU soft core
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shapool-coreFPGA core for SHA256d mining targeting Lattice iCE40 devices.
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Higan VerilogThis is a higan/Verilator co-simulation example/framework
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getting-startedList of ideas for getting started with TimVideos projects
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dpllA collection of phase locked loop (PLL) related projects
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Deep-DarkFantasyGlobal Dark Mode for ALL apps on ANY platforms.
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Symbiflow ExamplesExample designs showing different ways to use SymbiFlow toolchains.
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ElectronA mixed signal netlist language (pre-alpha)
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intfftkFully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
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CascadeA Just-In-Time Compiler for Verilog from VMware Research
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Open Fpga Verilog TutorialLearn how to design digital systems and synthesize them into an FPGA using only opensource tools
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Core jpegHigh throughput JPEG decoder in Verilog for FPGA
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UhdThe USRP™ Hardware Driver Repository
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Icestudio❄️ Visual editor for open FPGA boards
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Clash CompilerHaskell to VHDL/Verilog/SystemVerilog compiler
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mathUseful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
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Rsyocto🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)
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wbi2cWishbone controlled I2C controllers
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hwtVHDL/Verilog/SystemC code generator, simulator API written in python/c++
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dblclockfftA configurable C++ generator of pipelined Verilog FFT cores
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rapcoresRobotic Application Processor
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FPGA-USB-DeviceFPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.
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usbcorevA full-speed device-side USB peripheral core written in Verilog.
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EdalizeAn abstraction library for interfacing EDA tools
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Fake-SDcardImitate SDcard using FPGAs.
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RggenCode generation tool for configuration and status registers
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blarneyHaskell library for hardware description
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Icezum🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board
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RiscvRISC-V CPU Core (RV32IM)
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J1scA reimplementation of a tiny stack CPU
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FPGA NTP SERVERA FPGA implementation of the NTP and NTS protocols
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Apio🌱 Open source ecosystem for open FPGA boards
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ReduceronFPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.
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WbscopeA wishbone controlled scope for FPGA's
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Platformio CorePlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!
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Platformio Vscode IdePlatformIO IDE for VSCode: The next generation integrated development environment for IoT
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Beagle sdr gpsKiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
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IrohaIntermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
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ZbasicA bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
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Image ProcessingImage Processing Toolbox in Verilog using Basys3 FPGA
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HdlHDL libraries and projects
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FpOCFPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.
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eddr3mirror of https://git.elphel.com/Elphel/eddr3
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VerilogRepository for basic (and not so basic) Verilog blocks with high re-use potential
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SpinalhdlScala based HDL
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Mips CpuA MIPS CPU implemented in Verilog
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Hrm CpuHuman Resource Machine - CPU Design #HRM
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