GitPlanet

Cheap and reliable Node.js hosting starts at $3/month, and $1/month static HTML hosting

Created with love in Canada, visit hostnodejs.com today

Feel like to post an Ad? Learn Details
All Projects → marlls1989 → arv

marlls1989 / arv

Licence: GPL-2.0 license
ARV: Asynchronous RISC-V Go High-level Functional Model

Programming Languages

go
31211 projects - #10 most used programming language
c
50402 projects - #5 most used programming language
python
139335 projects - #7 most used programming language
Makefile
30231 projects
assembly
5116 projects

Labels

hardwareasynchronousprocessorriscvhdlrisc-vriscv32qdi

Projects that are alternatives of or similar to arv

Neorv32
A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
Stars: ✭ 106 (+488.89%)
Mutual labels:  hardware, processor, riscv, risc-v
rv32emu
RISC-V RV32I[MAC] emulator with ELF support
Stars: ✭ 61 (+238.89%)
Mutual labels:  riscv, risc-v, riscv32
Riscv Rust
RISC-V processor emulator written in Rust+WASM
Stars: ✭ 253 (+1305.56%)
Mutual labels:  processor, riscv, risc-v
Zelda.RISCV.Emulator
A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux
Stars: ✭ 18 (+0%)
Mutual labels:  riscv, risc-v, riscv32
Cores Swerv
SweRV EH1 core
Stars: ✭ 406 (+2155.56%)
Mutual labels:  processor, riscv, risc-v
yarvi
Yet Another RISC-V Implementation
Stars: ✭ 59 (+227.78%)
Mutual labels:  riscv, risc-v, riscv32
hero-sdk
⛔ DEPRECATED ⛔ HERO Software Development Kit
Stars: ✭ 21 (+16.67%)
Mutual labels:  riscv, risc-v, riscv32
Darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Stars: ✭ 1,062 (+5800%)
Mutual labels:  processor, riscv, risc-v
Cores Swerv El2
SweRV EL2 Core
Stars: ✭ 79 (+338.89%)
Mutual labels:  processor, riscv, risc-v
riscv em
Simple risc-v emulator, able to run linux, written in C.
Stars: ✭ 51 (+183.33%)
Mutual labels:  riscv, risc-v, riscv32
RiscvSpecFormal
The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.
Stars: ✭ 69 (+283.33%)
Mutual labels:  hardware, riscv
xeda
Cross EDA Abstraction and Automation
Stars: ✭ 25 (+38.89%)
Mutual labels:  hardware, hdl
riscv-meta
RISC-V Instruction Set Metadata
Stars: ✭ 33 (+83.33%)
Mutual labels:  riscv, risc-v
tree-core-cpu
A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
Stars: ✭ 22 (+22.22%)
Mutual labels:  processor, riscv
lipsi
Lipsi: Probably the Smallest Processor in the World
Stars: ✭ 64 (+255.56%)
Mutual labels:  hardware, processor
tree-core-ide
The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
Stars: ✭ 79 (+338.89%)
Mutual labels:  processor, riscv
platform-shakti
Shakti: development platform for PlatformIO
Stars: ✭ 26 (+44.44%)
Mutual labels:  riscv, risc-v
gateware-ts
Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
Stars: ✭ 83 (+361.11%)
Mutual labels:  hardware, hdl
icebreaker-amaranth-examples
This repository contains iCEBreaker examples for Amaranth HDL.
Stars: ✭ 26 (+44.44%)
Mutual labels:  hardware, hdl
nuclei-sdk
Nuclei RISC-V Software Development Kit
Stars: ✭ 65 (+261.11%)
Mutual labels:  riscv, risc-v
View All Similar Projects ➔

ARV Go High-level Functional Model

The Asynchronous RISC-V (ARV) is a 7-stage superscalar asynchronous processor model. It employs principles based on Communicating Sequential Processes (CSP), a paradigm suitable for modelling asynchronous circuits, while abstracting handshake protocols and data encoding details. In this way, the model is suitable as a specification for either quasi-delay insensitive (QDI) or bundled-data (BD) implementations.

This repository contains the ARV high-level executable model written in The Go Programming Language, which features channels and CSP-based goroutine constructs. The model describes the overall processor organisation, abstracting implementation details.

Installation Instructions

Intallation requires the following packages:

  • Go (minimal version 1.7)
  • Git (to fetch dependencies and the latest version)
  • GNU Toolchain for RISC-V (for building example code)

Instructions assume the model runs under some current Unix-like environment, e.g. Linux or MacOS.

Retrieve the latest version from the repository:

go get -u github.com/marlls1989/arv

In order to compile the code in samplecode and riscv-tests directories it is first necessary to get and install The GNU Toolchain for RISC-V, as described in:

git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
cd riscv-gnu-toolchain
mkdir build
cd build
../configure --with-arch=rv32ima --with-abi=ilp32
sudo make

Running Code in the Model

After completing the above installation, it is possible to compile and run the included sample code:

cd samplecode
make
arv -memfile hanoi.bin

The code provided in the samplecode directory is useful to write programs targeting the simulation platform.

To run the RISC-V Unit Test Suite, use the command set below:

git submodule init
git submodule update
cd riscv-tests
make
arv -memfile test.bin

For further options, including debug flags, use:

arv -h

Version History

  • v1.0 - First release described in Sartori's End of Term Work (In Brazilian Portuguese, this is called a "Trabalho de Conclusao de Curso" or TCC). The text of the TCC is in English.
  • v1.1 - First public release on Github, the register write-back mechanism is simplified and new performance counters are introduced. A conference paper containing results extracted from this version was approved for publication in the 24th IEEE International Conference on Electronics, Circuits and Systems.

Publications

  • SARTORI, M. L. L. ARV: Towards an Asynchronous Implementation of the RISC-V Architecture. End of Term Work. Computer Engineering - PUCRS, July 2017. 57p. (Presented and approved. Advisor: Ney Laert Vilar Calazans).
  • SARTORI, M. L. L.; CALAZANS, N. L. V. Go Functional Model for a RISC-V Asynchronous Organization - ARV. In: IEEE International Conference on Electronics, Circuits and Systems (ICECS'17), Batumi, 2017. Accepted for publication, final version in preparation.

Authors and License

The project started as an End of Term Work by Marcos Luiggi Lemos Sartori [email protected] at the Pontifical Catholic University of Rio Grande do Sul (PUCRS), RS, Brazil. It was developed within the Hardware Design Support Research Group (GAPH), advised by Prof. Ney Laert Vilar Calazans [email protected].

This work is licensed under GPLv2.

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].