The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

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Firesim

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

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platform-shakti

Shakti: development platform for PlatformIO

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icebreaker-amaranth-examples

This repository contains iCEBreaker examples for Amaranth HDL.

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gateware-ts

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

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Lbforth

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

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Shecc

A self-hosting and educational C compiler

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Scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

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Ustc Rvsoc

FPGA-based RISC-V CPU+SoC.

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Diosix

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

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Rars

RARS -- RISC-V Assembler and Runtime Simulator

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Meta Riscv

OpenEmbedded/Yocto layer for RISC-V Architecture

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Riscv Fs

F# RISC-V Instruction Set formal specification

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Potato

A simple RISC-V processor for use in FPGA designs.

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pygears

HW Design: A Functional Approach

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Ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

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tree-core-ide

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

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xeda

Cross EDA Abstraction and Automation

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riscv-meta

RISC-V Instruction Set Metadata

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tree-core-cpu

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

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Dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

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nuclei-sdk

Nuclei RISC-V Software Development Kit

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yatcpu

Yet another toy CPU.

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ravel

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Maxine Vm

Maxine VM: A meta-circular research VM

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NMSIS

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Jupiter

RISC-V Assembler and Runtime Simulator

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bx-docker

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

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KyogenRV

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Quasar 2.0: Chisel equivalent of SweRV-EL2