GitPlanet

Cheap and reliable Node.js hosting starts at $3/month, and $1/month static HTML hosting

Created with love in Canada, visit hostnodejs.com today

Feel like to post an Ad? Learn Details
All Projects → Triple-Z → COExperiment_Repo

Triple-Z / COExperiment_Repo

Licence: MIT license
支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017

Programming Languages

HTML
75241 projects
Verilog
626 projects
c
50402 projects - #5 most used programming language

Labels

cpumipsverilogcomputer-organization

Projects that are alternatives of or similar to COExperiment Repo

Mips Cpu
A MIPS CPU implemented in Verilog
Stars: ✭ 38 (+65.22%)
Mutual labels:  cpu, mips, verilog
Zipcpu
A small, light weight, RISC CPU soft core
Stars: ✭ 640 (+2682.61%)
Mutual labels:  cpu, verilog
Unicorn
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)
Stars: ✭ 4,934 (+21352.17%)
Mutual labels:  cpu, mips
Hrm Cpu
Human Resource Machine - CPU Design #HRM
Stars: ✭ 43 (+86.96%)
Mutual labels:  cpu, verilog
R8051
8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
Stars: ✭ 70 (+204.35%)
Mutual labels:  cpu, verilog
Riscv
RISC-V CPU Core (RV32IM)
Stars: ✭ 272 (+1082.61%)
Mutual labels:  cpu, verilog
Ustc Tmips
Stars: ✭ 6 (-73.91%)
Mutual labels:  cpu, mips
kianRiscV
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
Stars: ✭ 167 (+626.09%)
Mutual labels:  cpu, verilog
Darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Stars: ✭ 1,062 (+4517.39%)
Mutual labels:  cpu, verilog
J1sc
A reimplementation of a tiny stack CPU
Stars: ✭ 64 (+178.26%)
Mutual labels:  cpu, verilog
Ustc Rvsoc
FPGA-based RISC-V CPU+SoC.
Stars: ✭ 77 (+234.78%)
Mutual labels:  cpu, verilog
CSCvon8
A crazy small 8-bit CPU built with only seventeen 7400-series chips.
Stars: ✭ 86 (+273.91%)
Mutual labels:  cpu, verilog
ARM9-compatible-soft-CPU-core
This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
Stars: ✭ 42 (+82.61%)
Mutual labels:  cpu, verilog
Nontrivial Mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Stars: ✭ 417 (+1713.04%)
Mutual labels:  cpu, mips
TinyMIPS
The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.
Stars: ✭ 29 (+26.09%)
Mutual labels:  cpu, mips
Biriscv
32-bit Superscalar RISC-V CPU
Stars: ✭ 208 (+804.35%)
Mutual labels:  cpu, verilog
Vexriscv
A FPGA friendly 32 bit RISC-V CPU implementation
Stars: ✭ 1,041 (+4426.09%)
Mutual labels:  cpu, verilog
E200 opensource
This repository hosts the project for open-source hummingbird E203 RISC processor Core.
Stars: ✭ 1,909 (+8200%)
Mutual labels:  cpu, verilog
Mipt Mips
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
Stars: ✭ 250 (+986.96%)
Mutual labels:  cpu, mips
Kimera Vio Ros
ROS wrapper for Kimera-VIO
Stars: ✭ 182 (+691.3%)
Mutual labels:  cpu
View All Similar Projects ➔

Computer Organization Experiment

计算机组成原理实验

[TOC]

Last Revised: 7/1/2017

Project Assignment

Jump to source code directory

Jump to on board project directory

Instruction Set

Total: 36 + 9

Status Ins Type op func ALUctr Compare Jump RegDst ALUSrcB ALUSrcA MemtoReg RegWr MemWr ImmExt CopWr ByteExt iaddrtoNPC ManInput_raddr ManInput_shf
supported addu 000000 100001 0000 0 0 01 00 00 00 01 00 x 00 x 00
supported subu 000000 100011 0001 0 0 01 00 00 00 01 00 x 00 x 00
supported and 000000 100100 0010 0 0 01 00 00 00 01 00 x 00 x 00
supported or 000000 100101 0011 0 0 01 00 00 00 01 00 x 00 x 00
supported xor 000000 100110 0101 0 0 01 00 00 00 01 00 x 00 x 00
supported nor 000000 100111 0100 0 0 01 00 00 00 01 00 x 00 x 00
supported slt 000000 101010 1011 0 0 01 00 00 00 01 00 x 00 x 00
supported sltu 000000 101011 1010 0 0 01 00 00 00 01 00 x 00 x 00
supported addiu 001001 x 0000 0 0 00 01 00 00 01 00 00 00 x 00
supported slti 001010 x 1011 0 0 00 01 00 00 01 00 01 00 x 00
supported sltiu 001011 x 1010 0 0 00 01 00 00 01 00 00 00 x 00
supported andi 001100 x 0010 0 0 00 01 00 00 01 00 00 00 x 00
supported ori 001101 x 0011 0 0 00 01 00 00 01 00 00 00 x 00
supported xori 001110 x 0101 0 0 00 01 00 00 01 00 00 00 x 00
supported lui 001111 x 0110 0 0 00 01 10 00 01 00 00 00 x 00 x 0x00000010
supported sll 000000 000000 0110 0 0 01 00 01 00 01 00 x 00 x 00
supported srl 000000 000010 0111 0 0 01 00 01 00 01 00 x 00 x 00
supported sra 000000 000011 1000 0 0 01 00 01 00 01 00 x 00 x 00
supported sllv 000000 000100 0110 0 0 01 00 00 00 01 00 x 00 x 00
supported srlv 000000 000110 0111 0 0 01 00 00 00 01 00 x 00 x 00
supported srav 000000 000111 1000 0 0 01 00 00 00 01 00 x 00 x 00
supported lw 100011 x 0000 0 0 00 01 00 01 01 00 01 00 11 00
supported sw 101011 x 0000 0 0 x 01 00 x 00 01 01 00 11 00
supported lb 100000 x 0000 0 0 00 01 00 01 01 00 01 00 01 00
supported lbu 100100 x 0000 0 0 00 01 00 01 01 00 01 00 00 00
supported sb 101000 x 0000 0 0 00 01 00 x 00 01 01 00 10 00
supported beq 000100 x x 1 0 x 00 00 x 00 00 x 00 x 00
supported bne 000101 x x 1 0 x 00 00 x 00 00 x 00 x 00
supported bgez 000001 x x 1 0 x 00 00 x 00 00 x 00 x 00
supported bgtz 000111 x x 1 0 x 00 00 x 00 00 x 00 x 00
supported blez 000110 x x 1 0 x 00 00 x 00 00 x 00 x 00
supported bltz 000001 x x 1 0 x 00 00 x 00 00 x 00 x 00
supported j 000010 x x 0 1 x x x x 00 00 x 00 x 00
supported jr 000000 001000 x 0 1 x x 00 00 00 00 x 00 x 00
supported jalr 000000 001001 x 0 1 01 x 00 11 01 00 x 00 x 00
supported jal 000011 x x 0 1 10 x x 11 01 00 00 00 x 00 11111
Status Ins Type op func ALUctr Compare Jump RegDst ALUSrcB ALUSrcA MemtoReg RegWr MemWr ImmExt CopWr ByteExt iaddrtoNPC
supported mult 000000 011000 1001 0 0 x 00 00 x 00 00 x 00 x 00
supported mfhi 000000 010000 1101 0 0 01 00 00 00 01 00 x 00 x 00
supported mthi 000000 010001 1110 0 0 x x 00 x 00 00 x 00 x 00
supported mflo 000000 010010 1100 0 0 01 00 00 00 01 00 x 00 x 00
supported mtlo 000000 010011 1111 0 0 x x 00 x 00 00 x 00 x 00
supported mfc0 010000 x x 0 0 00 x x 10 01 00 x 00 x 00
supported mtc0 010000 x x 0 0 00 00 x 00 00 00 x 01 x 00
supported syscall 000000 001100 x 0 1 x x x 00 00 00 x 01 x 01
supported eret 010000 011000 x 0 1 x x x 00 00 00 x 01 x 01

Datapath Module

Control Module

Creator Module

Test Bench

Appendix

Project 2 Onboard Experiment

Jump to directory

Project 1

Jump to directory

单周期处理器开发

Instruction Set

Total: 12

Status Ins Type op func ALUctr Branch Jump RegDst ALUSrc MemtoReg RegWr MemWr ExtOp
supported addu 000000 100001 0000 0 0 1 0 0 1 0 x
supported add 000000 100000 0001 0 0 1 0 0 1 0 x
supported subu 000000 100011 1000 0 0 1 0 0 1 0 x
supported sub 000000 100010 1001 0 0 1 0 0 1 0 x
supported and 000000 100100 0010 0 0 1 0 0 1 0 x
supported or 000000 100101 0011 0 0 1 0 0 1 0 x
supported slt 000000 101010 1011 0 0 1 0 0 1 0 x
supported beq 000100 x 1001 1 0 x 0 x 0 0 x
supported sltu 000000 101011 1010 0 0 1 0 0 1 0 x
supported jump 000010 x x 0 1 x x x 0 0 x
supported lw 100011 x 0001 0 0 0 1 1 1 0 1
supported sw 101011 x 0001 0 0 x 1 x 0 1 1
supported ori 001101 x 0011 0 0 0 1 0 1 0 0

Datapath Module

Control Module

Creator Module

Test Bench

Appendix

Module Explanation

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].