Nontrivial MipsNonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
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Mutual labels: cpu, fpga, mips
Ustc Tmips Stars: ✭ 6 (-79.31%)
Mutual labels: cpu, mips, operating-system
Mips CpuA MIPS CPU implemented in Verilog
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Mutual labels: cpu, fpga, mips
Biriscv32-bit Superscalar RISC-V CPU
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Mutual labels: cpu, fpga
Ustc RvsocFPGA-based RISC-V CPU+SoC.
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Mutual labels: cpu, fpga
RiscboyPortable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
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Mutual labels: cpu, fpga
VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
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Mutual labels: cpu, fpga
COExperiment Repo支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017
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Mutual labels: cpu, mips
Forth CpuA Forth CPU and System on a Chip, based on the J1, written in VHDL
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Mutual labels: cpu, fpga
Advanced-xv6Modern improvements for MIT's xv6 OS
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Mutual labels: cpu, operating-system
managed ml systems and iotManaged Machine Learning Systems and Internet of Things Live Lesson
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Mutual labels: cpu, fpga
Cva6The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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Mutual labels: cpu, fpga
J1scA reimplementation of a tiny stack CPU
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Mutual labels: cpu, fpga
Neorv32A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
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Mutual labels: cpu, fpga
Darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
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Mutual labels: cpu, fpga
Mipt MipsCycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
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Mutual labels: cpu, mips
kianRiscVKianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
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Mutual labels: cpu, fpga
FPGACosmacELFA re-creation of a Cosmac ELF computer, Coded in SpinalHDL
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Mutual labels: cpu, fpga
tapascoThe Task Parallel System Composer (TaPaSCo)
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Mutual labels: fpga, fpga-soc
The Hack General Purpose ComputerUsing HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.
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Mutual labels: cpu, operating-system
