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VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
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ZipcpuA small, light weight, RISC CPU soft core
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Mips CpuA MIPS CPU implemented in Verilog
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E200 opensourceThis repository hosts the project for open-source hummingbird E203 RISC processor Core.
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R80518051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
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Hrm CpuHuman Resource Machine - CPU Design #HRM
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CSCvon8A crazy small 8-bit CPU built with only seventeen 7400-series chips.
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Ustc RvsocFPGA-based RISC-V CPU+SoC.
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J1scA reimplementation of a tiny stack CPU
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Darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
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COExperiment Repo支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017
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Mutual labels: cpu, verilog
Biriscv32-bit Superscalar RISC-V CPU
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kianRiscVKianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
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SpinalCryptoSpinalHDL - Cryptography libraries
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CoinHiveA nice friendly simple and easly customizable GUI for coinhives javascript miner to embed onto websites so users of your site can interact with features of the miner on every single page this javascript miner is to help those who have problems with advertisements/advertising/ads popups banners mobile redirects malvertising/malware etc and provid…
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indiciumPortable, advanced system information utility
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Hard-JPEG-LSFPGA-based JPEG-LS image compressor.
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MobileNet-in-FPGAGenerator of verilog description for FPGA MobileNet implementation
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