All Projects â†’ admk â†’ soap

admk / soap

Licence: MIT license
🎯 soap - Structural Optimisation of Arithmetic Programs

Programming Languages

python
139335 projects - #7 most used programming language
Isabelle
26 projects
VHDL
269 projects

Projects that are alternatives of or similar to soap

PandA-bambu
PandA-bambu public repository
Stars: ✭ 129 (+514.29%)
Mutual labels:  fpga, high-level-synthesis
hlsclt
A Vivado HLS Command Line Helper Tool
Stars: ✭ 35 (+66.67%)
Mutual labels:  fpga, high-level-synthesis
polyphony
Polyphony is Python based High-Level Synthesis compiler.
Stars: ✭ 90 (+328.57%)
Mutual labels:  fpga, high-level-synthesis
spector
Spector: An OpenCL FPGA Benchmark Suite
Stars: ✭ 38 (+80.95%)
Mutual labels:  fpga, design-space-exploration
basic-ecp5-pcb
Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
Stars: ✭ 71 (+238.1%)
Mutual labels:  fpga
Xrt
Xilinx Run Time for FPGA
Stars: ✭ 236 (+1023.81%)
Mutual labels:  fpga
Icicle
32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs
Stars: ✭ 234 (+1014.29%)
Mutual labels:  fpga
Hastlayer Sdk
Turning .NET assemblies into FPGA hardware for faster execution and lower power usage. See the Readme and https://hastlayer.com.
Stars: ✭ 226 (+976.19%)
Mutual labels:  fpga
FPGAmp
720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
Stars: ✭ 190 (+804.76%)
Mutual labels:  fpga
managed ml systems and iot
Managed Machine Learning Systems and Internet of Things Live Lesson
Stars: ✭ 35 (+66.67%)
Mutual labels:  fpga
SpinalDev
Docker Development Environment for SpinalHDL
Stars: ✭ 17 (-19.05%)
Mutual labels:  fpga
Blueoil
Bring Deep Learning to small devices
Stars: ✭ 244 (+1061.9%)
Mutual labels:  fpga
Awesome-Retro-Docs
A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.
Stars: ✭ 128 (+509.52%)
Mutual labels:  fpga
Convolution network on fpga
CNN acceleration on virtex-7 FPGA with verilog HDL
Stars: ✭ 236 (+1023.81%)
Mutual labels:  fpga
vga-clock
Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Stars: ✭ 48 (+128.57%)
Mutual labels:  fpga
Axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Stars: ✭ 227 (+980.95%)
Mutual labels:  fpga
fpga-docker
Tools for running FPGA vendor toolchains with Docker
Stars: ✭ 54 (+157.14%)
Mutual labels:  fpga
kianRiscV
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
Stars: ✭ 167 (+695.24%)
Mutual labels:  fpga
Xilinx axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
Stars: ✭ 251 (+1095.24%)
Mutual labels:  fpga
Basic verilog
Must-have verilog systemverilog modules
Stars: ✭ 247 (+1076.19%)
Mutual labels:  fpga

SOAP

SOAP is a tool for automatically exploring optimisations to a numerical C program, so that when it is synthesized into an FPGA implementation, the error, area, and latency of the implementation are minimised.

Installation

Requirements: * Python3

$ pip install -r requirements.txt

Usage

./soapy --help

Benchmark Results

Available here.

Caveat

The tool is still in its early stage, so please expect many rough edges and bugs. Please feel free to file an issue when you encounter a bug.

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].