330 Open source projects that are alternatives of or similar to soap

Polyphony is Python based High-Level Synthesis compiler.

PandA-bambu public repository

A Vivado HLS Command Line Helper Tool

Spector: An OpenCL FPGA Benchmark Suite

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Fletcher: A framework to integrate FPGA accelerators with Apache Arrow

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Docker Development Environment for SpinalHDL

32-bit Superscalar RISC-V CPU

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

Xilinx Run Time for FPGA

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

Turning .NET assemblies into FPGA hardware for faster execution and lower power usage. See the Readme and https://hastlayer.com.

A simple, basic, formally verified UART controller

Managed Machine Learning Systems and Internet of Things Live Lesson

Open source ultrasound processing modules and building blocks

Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

An Open-source FPGA IP Generator

i8080 precise replica in Verilog, based on reverse engineering of real die

Recipe for FPGA cooking

Bring Deep Learning to small devices

MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

PlutoSDR Firmware

CNN acceleration on virtex-7 FPGA with verilog HDL

Build Customized FPGA Implementations for Vivado

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Space Invaders game implemented with VHDL

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

All open source file and project for OpenFPGAduino project

A curated list of awesome open source hardware design tools

LicheeTang 蜂鸟E203 Core

80186 compatible SystemVerilog CPU core and FPGA reference design

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

A collection of extensions for Vivado HLS and Intel FPGA OpenCL to improve developer quality of life.

Notes on the Red Pitaya Open Source Instrument

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Tools for running FPGA vendor toolchains with Docker

a simple and cheap vector network analyzer, including support software

Verilog Generator of Neural Net Digit Detector for FPGA

Connectal is a framework for software-driven hardware development.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)

An Open Source Deep Learning Inference Engine Based on FPGA

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

A utility for Composing FPGA designs from Peripherals

Must-have verilog systemverilog modules

FPGA/hardware design of openwifi

DaCe - Data Centric Parallel Programming

FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian10 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc)

Bus bridges and other odds and ends

Sturdy is a library for developing sound static analyses in Haskell.