GitPlanet

Cheap and reliable Node.js hosting starts at $3/month, and $1/month static HTML hosting

Created with love in Canada, visit hostnodejs.com today

Feel like to post an Ad? Learn Details
All Projects → mattvenn → vga-clock

mattvenn / vga-clock

Licence: other
Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Programming Languages

Verilog
626 projects

Labels

fpgasimulationrtlverilog

Projects that are alternatives of or similar to vga-clock

Hard-JPEG-LS
FPGA-based JPEG-LS image compressor.
Stars: ✭ 52 (+8.33%)
Mutual labels:  fpga, rtl, verilog
blarney
Haskell library for hardware description
Stars: ✭ 81 (+68.75%)
Mutual labels:  fpga, rtl, verilog
hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Stars: ✭ 145 (+202.08%)
Mutual labels:  fpga, rtl, verilog
Logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Stars: ✭ 149 (+210.42%)
Mutual labels:  fpga, rtl, verilog
Spinalhdl
Scala based HDL
Stars: ✭ 696 (+1350%)
Mutual labels:  fpga, rtl, verilog
SpinalCrypto
SpinalHDL - Cryptography libraries
Stars: ✭ 36 (-25%)
Mutual labels:  fpga, rtl, verilog
SpinalDev
Docker Development Environment for SpinalHDL
Stars: ✭ 17 (-64.58%)
Mutual labels:  fpga, rtl, verilog
FPGA-USB-Device
FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.
Stars: ✭ 29 (-39.58%)
Mutual labels:  fpga, rtl, verilog
Verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
Stars: ✭ 296 (+516.67%)
Mutual labels:  fpga, rtl, verilog
Cores
Various HDL (Verilog) IP Cores
Stars: ✭ 271 (+464.58%)
Mutual labels:  fpga, rtl, verilog
sphinxcontrib-hdl-diagrams
Sphinx Extension which generates various types of diagrams from Verilog code.
Stars: ✭ 37 (-22.92%)
Mutual labels:  fpga, rtl, verilog
Rggen
Code generation tool for configuration and status registers
Stars: ✭ 54 (+12.5%)
Mutual labels:  fpga, rtl, verilog
virtio
Virtio implementation in SystemVerilog
Stars: ✭ 38 (-20.83%)
Mutual labels:  fpga, rtl, verilog
Fpga readings
Recipe for FPGA cooking
Stars: ✭ 164 (+241.67%)
Mutual labels:  fpga, rtl, verilog
cnn open
A hardware implementation of CNN, written by Verilog and synthesized on FPGA
Stars: ✭ 157 (+227.08%)
Mutual labels:  fpga, rtl, verilog
Fake-SDcard
Imitate SDcard using FPGAs.
Stars: ✭ 26 (-45.83%)
Mutual labels:  fpga, rtl, verilog
Darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Stars: ✭ 1,062 (+2112.5%)
Mutual labels:  fpga, rtl, verilog
Ustc Rvsoc
FPGA-based RISC-V CPU+SoC.
Stars: ✭ 77 (+60.42%)
Mutual labels:  fpga, rtl, verilog
Openfpgaduino
All open source file and project for OpenFPGAduino project
Stars: ✭ 137 (+185.42%)
Mutual labels:  fpga, verilog
Openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design
Stars: ✭ 2,257 (+4602.08%)
Mutual labels:  fpga, verilog
View All Similar Projects ➔

VGA Clock

simple project to show the time on a 640x480 VGA display.

vga clock

Simulation instructions

Ensure that you have libsdl2-dev and verilator installed.

sudo apt-get install libsdl2-dev libsdl2-image-dev verilator

To run the simulation use the following commands:

cd rtl
make verilator && ./obj_dir/Vvga_clock

fb_verilator

Use the h, m and s keys to increment the hour, minute and second counters respectively.

FPGA Build instructions

It's setup to run on 1 Bit Squared icebreaker with my VGA pmod plugged into pmod1a.

type

make prog

to build & upload to the icebreaker

FPGA utilisation

using logLUTs to record resource usage and max frequency over commits:

luts

ASIC utilisation

https://www.zerotoasiccourse.com/post/vga_clock/

using the Skywater/Google 130nm process and OpenLane

  • copy contents of rtl directory to designs/vga_clock/src/
  • remove digit_tb.v and top_tb.v from designs/vga_clock/src/ (I am working on separating test and rtl)
  • copy asic/config.tcl to designs/vga_clock/
  • inside the docker environment:
    • run ./flow.tcl -init_design_config -design vgaclock
    • run ./flow.tcl -design vga_clock

This results in a routed design that uses 180x180 microns.

See asic/Makefile for some rules that start the docker and show the finished GDS in magic or klayout.

full die

zoom top left

License

This software and hardware is licensed under the Apache License version 2

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].