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Mutual labels: verilog
R80518051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
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Mutual labels: verilog
usbcorevA full-speed device-side USB peripheral core written in Verilog.
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Mutual labels: verilog
tree-sitter-tomlTOML grammar for tree-sitter
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Mutual labels: tree-sitter
verilog-coding-styleVerilog (SystemVerilog) coding style
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Mutual labels: verilog
eddr3mirror of https://git.elphel.com/Elphel/eddr3
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Mutual labels: verilog
CSCvon8A crazy small 8-bit CPU built with only seventeen 7400-series chips.
Stars: ✭ 86 (+75.51%)
Mutual labels: verilog
nvim-yatiYet another tree-sitter powered indent plugin for Neovim.
Stars: ✭ 60 (+22.45%)
Mutual labels: tree-sitter
tree-sitter-tlaplusA tree-sitter grammar for TLA+
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Mutual labels: tree-sitter
pcievhostPCIe (1.0a to 2.0) Virtual host model for verilog
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Mutual labels: verilog
rules verilatorBazel build rules for Verilator
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Mutual labels: verilog
FpOCFPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.
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Mutual labels: verilog
FPGA NTP SERVERA FPGA implementation of the NTP and NTS protocols
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Mutual labels: verilog
verismithVerilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
Stars: ✭ 74 (+51.02%)
Mutual labels: verilog
tree-sitter-markdownA markdown grammar for tree-sitter
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Mutual labels: tree-sitter
SwiftTreeSitterSwift wrappers for the tree-sitter incremental parsing system
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Mutual labels: tree-sitter
symbolatorHDL symbol generator
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Mutual labels: verilog
cocotb-busPre-packaged testbenching tools and reusable bus interfaces for cocotb
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Mutual labels: verilog
ruby-tree-sitterRuby bindings to tree-sitter
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Mutual labels: tree-sitter
rust-tree-sitterRust bindings to Tree-sitter
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Mutual labels: tree-sitter