dockerScripts to build and use docker images including GHDL
Stars: ✭ 27 (+35%)
Mutual labels: vhdl, verilog, testbench
symbolatorHDL symbol generator
Stars: ✭ 123 (+515%)
Mutual labels: vhdl, verilog, hdl
vboardVirtual development board for HDL design
Stars: ✭ 32 (+60%)
Mutual labels: vhdl, verilog, hdl
xedaCross EDA Abstraction and Automation
Stars: ✭ 25 (+25%)
Mutual labels: vhdl, verilog, hdl
verilog-vcd-parserA parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
Stars: ✭ 46 (+130%)
Mutual labels: vhdl, verilog
vscode-terosHDLVHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Stars: ✭ 325 (+1525%)
Mutual labels: vhdl, verilog
gateware-tsHardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
Stars: ✭ 83 (+315%)
Mutual labels: verilog, hdl
hdl-toolsFacilitates building open source tools for working with hardware description languages (HDLs)
Stars: ✭ 56 (+180%)
Mutual labels: verilog, hdl
virtioVirtio implementation in SystemVerilog
Stars: ✭ 38 (+90%)
Mutual labels: verilog, hdl
sphinxcontrib-hdl-diagramsSphinx Extension which generates various types of diagrams from Verilog code.
Stars: ✭ 37 (+85%)
Mutual labels: verilog, hdl
SpinalCryptoSpinalHDL - Cryptography libraries
Stars: ✭ 36 (+80%)
Mutual labels: vhdl, verilog
vim-hdlVim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
Stars: ✭ 59 (+195%)
Mutual labels: vhdl, verilog
SpinalDevDocker Development Environment for SpinalHDL
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Mutual labels: vhdl, verilog
fpga-dockerTools for running FPGA vendor toolchains with Docker
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Mutual labels: vhdl, verilog
DegateOpen source software for chip reverse engineering.
Stars: ✭ 156 (+680%)
Mutual labels: vhdl, verilog
TinytpuImplementation of a Tensor Processing Unit for embedded systems and the IoT.
Stars: ✭ 153 (+665%)
Mutual labels: vhdl, verilog
formal hw verificationTrying to verify Verilog/VHDL designs with formal methods and tools
Stars: ✭ 32 (+60%)
Mutual labels: vhdl, verilog
Hdl checkerRepurposing existing HDL tools to help writing better code
Stars: ✭ 103 (+415%)
Mutual labels: vhdl, verilog
async fifoA dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Stars: ✭ 117 (+485%)
Mutual labels: verilog, hdl