704 Open source projects that are alternatives of or similar to Computer-Architecture-Task-2

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

RISC-V CPU Core (RV32IM)

a realtime plotting utility for terminal/console with data input from stdin

FPGA-based RISC-V CPU+SoC.

RISC-V processor emulator written in Rust+WASM

All CPU and MCU documentation in one place

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

32-bit Superscalar RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

F# RISC-V Instruction Set formal specification

The Hybrid Task Graph Scheduler API

RISC-V CPU Core

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

Yet another toy CPU.

Show Me A Graph - Command Line Graphing

A lightweight data processing framework for Apache Spark

开源运维平台设计及开发样例、CMS、RBAC、python开发教程、管理系统设计及开发样例、jenkinsfile(pipeline)/ansible使用教程，一切想到的，想不到的，应有尽有

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

FreeCAD - flamingo workbench

Highly portable Zilog Z80 CPU emulator written in ANSI C

TypeScript/JavaScript utilities for those who don't like utilities

🐈 🐈 🐈 Running Cat

Implementation of the MC6809 CPU in Python (Extracted from https://github.com/jedie/DragonPy project)

QEMU platform SBI support implementation, using RustSBI

No description or website provided.

Implementation of LIBELAS in cuda.

基于Spring Cloud的微服务业务框架

Project Planeverb is a CPU based real-time wave-based acoustics engine for games. It comes with an integration with the Unity Engine.

A macOS application displaying the thermal, voltage and current sensor values.

Multi-Platform C code Library for EVE graphics controllers from FTDI / Bridgetek (FT810, FT811, FT812, FT813, BT815, BT816, BT817, BT818)

Generate beautiful documentation for your data pipelines in markdown format

A Folding@Home Docker container with GPU support

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

Generic but comprehensive pipeline for prokaryotic genome annotation and interrogation with interactive reports and shiny app.

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

Precision HLA typing from next-generation sequencing data

A simple script to log Linux CPU and memory usage (using top or pidstat command) over time and output an Excel- or OpenOfficeCalc-friendly report

ARV: Asynchronous RISC-V Go High-level Functional Model

Bioinformatics pipeline for SARS-CoV-2 sequencing at CZ Biohub

MDEPX — A BSD-style RTOS

cpu command in Go, inspired by the Plan 9 cpu command

hub.docker.com/repository/docker/davidburela/riscv-emulator

A build system for modular development in Salesforce, delivered as a sfdx plugin that can be implemented in any CI/CD system of choice

💻 Learn Bash streams, pipelines and redirection, from beginner to advanced.

dnaPipeTE (for de-novo assembly & annotation Pipeline for Transposable Elements), is a pipeline designed to find, annotate and quantify Transposable Elements in small samples of NGS datasets. It is very useful to quantify the proportion of TEs in newly sequenced genomes since it does not require genome assembly and works on small datasets (< 1X).

CPU and home computer project

RNA-seq analysis pipeline for detection gene-fusions

MTBseq is an automated pipeline for mapping, variant calling and detection of resistance mediating and phylogenetic variants from illumina whole genome sequence data of Mycobacterium tuberculosis complex isolates.

Fun functional programming with pipelinable functions

Central Processing Unit Information Gathering Tool

Renderer using C++, Embree and USD to achieve Path Tracing techniques on the CPU

Old specification for Hack pipes in JavaScript. Please go to the new specification.

Pytorch Implementation of GoEmotions 😍😢😱

Nextflow RNA-Seq Best Practice analysis pipeline, used at the SciLifeLab National Genomics Infrastructure.

Code, documentation, schematics, notes for my Ben Eater inspired breadboard computer and emulator

Darknet on OpenCL Convolutional Neural Networks on OpenCL on Intel & NVidia & AMD & Mali GPUs for macOS & GNU/Linux

VIRify: detection of phages and eukaryotic viruses from metagenomic and metatranscriptomic assemblies

Designed with Micriμm's renowned quality, scalability and reliability, the purpose of μC/ CPU is to provide a clean, organized ANSI C implementation of each processor's/compiler's hardware-dependent.