93 Open source projects that are alternatives of or similar to K210 Hal

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

RISC-V Instruction Set Metadata

计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位

Freedom U Software Development Kit (FUSDK)

Embedded Rust's Peripheral Access Crate for BL602 microcontrollers

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Shakti: development platform for PlatformIO

Simple RISC-V 3-stage Pipeline in Chisel

CKB's vm, based on open source RISC-V ISA

A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python

F# RISC-V Instruction Set formal specification

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Rocket Chip Generator

An unofficial reference sheet for RISC-V.

Reference implementation for the book "Writing a RISC-V Emulator in Rust".

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

Rust version of THU uCore OS. Linux compatible.

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

OpenEmbedded/Yocto layer for RISC-V Architecture

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

homebrew (macOS) packages for RISC-V toolchain

riscv资料、论文等

SweRV EL2 Core

FPGA-based RISC-V CPU+SoC.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Riscy Processors - Open-Sourced RISC-V Processors

FPGA 101 - Workshop materials

Tests for example Rocket Custom Coprocessors

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A FPGA friendly 32 bit RISC-V CPU implementation

Tengine is a lite, high performance, modular inference engine for embedded device

ncnn is a high-performance neural network inference framework optimized for the mobile platform