WebRISC-VWebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
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Icarus VerilogThis repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
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PulsarOpen source VFX pipeline tool
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vcdvcdPython Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
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SBTCVM-Gen2-9SBTCVM is a virtual machine implementation of a balanced ternary (base 3) computer. Features several compiled languages for ternary software development.
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nodejs-docker-exampleAn example of how to run a Node.js project in Docker in a Buildkite pipeline
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doepipelineA python package for optimizing processing pipelines using statistical design of experiments (DoE).
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hms-av-pipeline-demoHUAWEI AV Pipeline Kit sample code project, which contains the Java sample code to implement functions like video playback, video super-resolution and media asset management. C++ sample code is contained for calling MediaFilter to use the sound event detection plugin.
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nanoseqNanopore demultiplexing, QC and alignment pipeline
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pdp6PDP-6 Emulator
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fpga-nnNN on FPGA
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bookmarksA PySide2 based file and asset manager for animation and CG productions.
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targets-minimalA minimal example data analysis project with the targets R package
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EDTAExtensive de-novo TE Annotator
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k3ai-coreK3ai-core is the core library for the GO installer. Go installer will replace the current bash installer
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scrnaseqA single-cell RNAseq pipeline for 10X genomics data
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veriflaFork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm
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redundansRedundans is a pipeline that assists an assembly of heterozygous/polymorphic genomes.
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SpinalCryptoSpinalHDL - Cryptography libraries
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skinnerSkin export / import tools for Autodesk Maya
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streamalgExtensible stream pipelines with object algebras.
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MNISTHandwritten digit recognizer using a feed-forward neural network and the MNIST dataset of 70,000 human-labeled handwritten digits.
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Verilog-Gadget🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.
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pipenpipen - A pipeline framework for python
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pypiperPython toolkit for building restartable pipelines
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plumbingThis repo holds configuration for infrastructure used across the tektoncd org 🏗️
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hyperdriveExtensible streaming ingestion pipeline on top of Apache Spark
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modelboxA high performance, high expansion, easy to use framework for AI application. 为AI应用的开发者提供一套统一的高性能、易用的编程框架,快速基于AI全栈服务、开发跨端边云的AI行业应用。
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Geoweavera web system to allow users to automatically record history and manage complicated scientific workflows in web browsers involving the online spatial data facilities, high-performance computation platforms, and open-source libraries.
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eventkitEvent-driven data pipelines
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krshA declarative KubeFlow Management Tool
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yarviYet Another RISC-V Implementation
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ARM9-compatible-soft-CPU-coreThis ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
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Apos.ContentContent builder library for MonoGame.
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reskitA library for creating and curating reproducible pipelines for scientific and industrial machine learning
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LogHubNo description or website provided.
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pipelineSpline is a tool that is capable of running locally as well as part of well known pipelines like Jenkins (Jenkinsfile), Travis CI (.travis.yml) or similar ones.
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cloud-native-pipelinesCloud-native pipelines leveraging Concourse, Pivotal Build Service and Spinnaker to deploy apps
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Hard-JPEG-LSFPGA-based JPEG-LS image compressor.
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unity-build-pipelineCustom BASH script for build, archive, export and upload APK and IPA to server with Telegram notification
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vboardVirtual development board for HDL design
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formal hw verificationTrying to verify Verilog/VHDL designs with formal methods and tools
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piper-nfRNA mapping pipeline
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vericertA formally verified high-level synthesis tool based on CompCert and written in Coq.
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ngs pipelineExome/Capture/RNASeq Pipeline Implementation using snakemake
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vim-hdlVim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
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dropPipeline to find aberrant events in RNA-Seq data, useful for diagnosis of rare disorders
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SeqToolsA python library to manipulate and transform indexable data (lists, arrays, ...)
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DFFRAMStandard Cell Library based Memory Compiler using FF/Latch cells
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smagShow Me A Graph - Command Line Graphing
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pypelyMake your data processing easy
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