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All Projects → Cloud-V → DFFRAM

Cloud-V / DFFRAM

Licence: Apache-2.0 license
Standard Cell Library based Memory Compiler using FF/Latch cells

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Verilog
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verilogvlsivlsi-physical-designvlsi-circuitselectronics-designasic-design

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DFFRAM Compiler

Open in Google Colab

License: Apache 2.0 CI Status Invite to the Skywater PDK Slack Code Style: Black

Standard Cell Library based Memory Compiler using DFF/Latch cells.

✨ Quick Usage

You can try the Google Colaboratory, but also...

Get Docker, set it up nicely, then, in your terminal:

pip3 install --user --no-cache-dir --upgrade ./requirements.txt
./dffram.py -s 32x32

If all goes well, you've placed your first register file!

Overview

The objective of this project is to develop a DFF/Latch-based RAM, Register File and Cache custom compilation flow that utilizes standard cell libraries following a standard ASIC (Application Specific Integrated Circuit) implementation approach. Different views (HDL netlist, HDL functional models, LEF, GDS, Timing, …) are all generated for a given size configuration.

The layout targets highly compact designs (85%+) as the cells are placed on the floor plan using a custom placer. Moreover, the custom placer ensures that the routing will be relatively simple. Currently, the compiler uses OpenROAD routers to route the macros with great success.

The Compiler relies on basic building blocks to construct the layout of different RAM/RF/Cache configurations. Check the compiler documentation for more info. The following shows how a 32x32 memory (DFF based) is constructed.

The generated layouts by the DFFRAM compilers for RAM32 as well as its building blocks are as follows:

  • BYTE

         drawing

  • WORD (32-bit) A Word; placed and routed, metal only, no outline

  • RAM8 (32x8) 8 Words; placed and routed

  • RAM32 (32x32) 32 Words; placed and routed

Currently, the can compiler generate the layout of the following configurations:

  • RAM
    • 32 words with byte write enable (1RW and 1RW1R).
    • 128 words with byte write enable (1RW and 1RW1R).
    • 256 words with byte write enable (1RW and 1RW1R).
    • 512 words with byte write enable (1RW and 1RW1R).
    • 1024 words with byte write enable (1RW and 1RW1R).
    • 2048 words with byte write enable (1RW and 1RW1R).
  • Register File
    • 32 x 32-bit words (2R1W)

The layout of 2048x32 (8 Kbytes) RAM as generated by the compiler is shown below: 8kbytes

The OpenLane/ folder will contain good known OpenLane configurations to build DFFRAM different macros.

File Structure

  • .github contains files for GitHub actions.
  • docs/ contains documentation (😮)
  • rtl/ contains RTL RAM file generators for benchmarking and comparison purposes.
  • platforms/ contains PDK-specific files:
    • <pdk-name>/
      • <scl-name>/
        • _building_blocks/ contains a hierarchy of building blocks supported by the compiler.
  • placeram/ is the custom placer Python module.
  • scripts/ has assisting scripts used by the flow.
  • dffram.py is the compilation flow going from building blocks to LVS.

Comparisons

The following table compares the areas and bit densities of RAM macros generated using different means.

Size1 OpenRAM2 DFFRAM Compiler DFFRAM/OpenLane RTL/OpenLane
Dim WxH (μm) Bit Density (bits/mm2) Dim WxH (μm) Bit Density (bits/mm2) Dim WxH (μm) Bit Density (bits/mm2) Dim WxH (μm) Bit Density (bits/mm2)
512 bytes N/A N/A 395.6 x 388.96 26,619 TBD TBD 680.25 x 690.97 8,714
1 kbytes 386 x 456 46,541 788.44 x 394.4 26,344 TBD TBD 1,050 x 1,060 7,360
2 kbytes 659.98 x 398.18 62,372 793.5 x 783.36 26,358 TBD TBD 1,439.615 x 1,450.335 7,847
4 kbytes 670.86 x 651.14 75,014 1,584.24 x 788.8 26,196 TBD TBD 2,074 x 2,085 7,578
8 kbytes N/A N/A 1,589 x 1,572 26,229 TBD TBD 2,686.610 x 2,697.330 9,043

1 All support 32-bit word reads and 1, 2, and 4 bytes writes.
2 Values are based on the original layout produced by the compiler. OpenRAM macros are typically wrapped to be useful w/ automated PnR ASIC flows.

⚖️ Copyright and Licensing

Copyright ©2020-2021 The American University in Cairo and the Cloud V Project.

Licensed under the Apache License, Version 2.0 (the "Open Source License"); you may not use this file except in compliance with the Open Source License. You may obtain a copy of the Open Source License at the root of this repository (see the file 'License') or at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the Open Source License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the Open Source License for the specific language governing permissions and limitations under the Open Source License.

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].