689 Open source projects that are alternatives of or similar to Opentimer

Verilog to Routing -- Open Source CAD Flow for FPGA Research

A powerful, innovative and intuitive EDA tool for everyone!

An abstraction library for interfacing EDA tools

Cross EDA Abstraction and Automation

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Library for VLSI CAD Design Useful parsers and solvers' api are implemented.

Toolset to capture, simulate, synthesize and verify graph models

Gdstk (GDSII Tool Kit) is a C++/Python library for creation and manipulation of GDSII and OASIS files.

Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

ACT hardware description language and core tools.

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

OpenROAD's unified application implementing an RTL-to-GDS Flow

Library for working with KiCAD file formats

Code generation tool for configuration and status registers

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Open source design files for the TinyFPGA B-Series boards.

🛠️ 📊 Tools for Exploring and Comparing Data Frames

Netgen/NGSolve is a high performance multiphysics finite element software. It is widely used to analyze models from solid mechanics, fluid dynamics and electromagnetics. Due to its flexible Python interface new physical equations and solution algorithms can be implemented easily.

Functionalities in Excel translated to Python

Notes on the Red Pitaya Open Source Instrument

LibreCAD 3 is a next generation 2D CAD application written to be modular, with a core independent from GUI toolkits. Scripting is possible with Lua.

Verilog I2C interface for FPGA implementation

A Compiler for the Popr Language

A hyperparameter optimization and data collection toolbox for convenient and fast prototyping of machine-learning models.

Verilog SDRAM memory controller

一步一步写MIPS CPU

SUNDIALS is a SUite of Nonlinear and DIfferential/ALgebraic equation Solvers. This is a mirror of current releases, and development will move here eventually. Pull requests are welcome for bug fixes and minor changes.

Next generation FEniCS problem solving environment

32-bit Superscalar RISC-V CPU

A day to day plan for this challenge. Covers both theoritical and practical aspects

3D CAD viewer and converter based on Qt + OpenCascade

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Python module for creating GDSII stream files, usually CAD layouts.

Verilog Generator of Neural Net Digit Detector for FPGA

SystemVerilog parser library fully complient with IEEE 1800-2017

build BREP Solids with OpenCascade and NodeJS - 3D Modeling

CadQuery GUI editor based on PyQT

CHIP-8 console on FPGA

MetroBoy - A playable, circuit-level simulation of an entire Game Boy

自动化数据探索分析和智能可视化设计应用. Automatic insights discovery and visualization for data analysis.

A curated list of awesome parallel computing resources

Automatic parallelization of Python/NumPy, C, and C++ codes on Linux and MacOSX

A Verilog HDL model of the MOS 6502 CPU

BaseJump STL: A Standard Template Library for SystemVerilog

FPGA,Verilog,Python

Must read research papers and links to tools and datasets that are related to using machine learning for compilers and systems optimisation

FPGA/hardware design of openwifi

A message-passing distributed computing framework for node.js

Bigmachine is a library for self-managing serverless computing in Go

FPGA-based Nintendo Entertainment System Emulator

A framework for GPU based high-performance medical image processing and visualization

Recipe for FPGA cooking

2D/3D geometry package for Elm

Computational Fluid Dynamics (CFD) for FreeCAD based on OpenFOAM solver

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

Hardware implementation of the SHA-256 cryptographic hash function

AutoCAD Code Pack: A powerful library that helps you to develop AutoCAD plugins using the AutoCAD .NET API

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)