569 Open source projects that are alternatives of or similar to ARM9-compatible-soft-CPU-core

FPGA-based RISC-V CPU+SoC.

A small, light weight, RISC CPU soft core

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A MIPS CPU implemented in Verilog

RISC-V CPU Core (RV32IM)

A reimplementation of a tiny stack CPU

Human Resource Machine - CPU Design #HRM

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

A FPGA friendly 32 bit RISC-V CPU implementation

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

32-bit Superscalar RISC-V CPU

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

A nice friendly simple and easly customizable GUI for coinhives javascript miner to embed onto websites so users of your site can interact with features of the miner on every single page this javascript miner is to help those who have problems with advertisements/advertising/ads popups banners mobile redirects malvertising/malware etc and provid…

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

MERA 400 emulator

Generator of verilog description for FPGA MobileNet implementation

Profit Switching Miner For HiveOS/Linux- OLD VERSION: Project Moved To SWARM! https://github.com/MaynardMiner/SWARM

Get usage and health data about your Node.js process.

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

FAST-9 Accelerator for Corner Detection

The free, open-source Content Blocker for 32- and 64-bit iOS devices

Perf monitoring CLI tool for Apple Silicon

Virtual development board for HDL design

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

The Hybrid Task Graph Scheduler API

A Hardware Construct Language

MOS6581 SID chip emulator in SystemVerilog

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

SpinalHDL - Cryptography libraries

Lattice iCE40: development platform for PlatformIO

Portable, advanced system information utility

A fast and simple ARM Simulator made for education based upon Unicorn and Keystone engines

FPGA-based JPEG-LS image compressor.

Node.js in-process collectors for Instana

ROS node that publishes all nodes' CPU and memory usage

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Outputs current CPU core and package temperatures on macOS.

Get CPU, Memory and Network informations of the running OS and its processes

Sphinx Extension which generates various types of diagrams from Verilog code.

ncnn android benchmark app

PDP-6 Emulator

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

💾 A minimal, experimental and "toy" monolithic kernel to learn about OS development // Work In Progress

Programmable multichannel ADPCM decoder for FPGA

A programming language for FPGAs.

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU

Cross EDA Abstraction and Automation

A computer that uses nothing but human resources

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

Python script and a PyQt5 program to monitor ram and cpu usage along with disk usage.

Simple and Effective Face Detector, based on Progressive Calibration Networks (PCN) which is an accurate rotation-invariant face detector running at real-time speed on CPU, published in CVPR 2018.

LMC emulator written in Rust

C++ extension implementation of RoIAlign & RolPool (both GPU and CPU) for PyTorch

ROI Coin "ROI Coin Is Different"

Yet Another Tetris on FPGA Implementation