Biriscv32-bit Superscalar RISC-V CPU
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Mutual labels: fpga, verilog, risc-v
getting-startedList of ideas for getting started with TimVideos projects
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spu32Small Processing Unit 32: A compact RV32I CPU written in Verilog
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super-miyamoto-sprintHomebrew game for homebrew FPGA game console
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Darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
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Mutual labels: fpga, verilog, risc-v
Icestation 32Compact FPGA game console
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yarviYet Another RISC-V Implementation
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RiscvRISC-V CPU Core (RV32IM)
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Platformio CorePlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!
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Mutual labels: fpga, verilog, risc-v
Ustc RvsocFPGA-based RISC-V CPU+SoC.
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Tang e203 miniLicheeTang 蜂鸟E203 Core
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Icicle32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs
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Red Pitaya NotesNotes on the Red Pitaya Open Source Instrument
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ics-adpcmProgrammable multichannel ADPCM decoder for FPGA
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yafpgatetrisYet Another Tetris on FPGA Implementation
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fpga-dockerTools for running FPGA vendor toolchains with Docker
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Mutual labels: fpga, verilog
FPGA ThreeLevelStorage【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。
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Mutual labels: fpga, verilog
Openwifi HwFPGA/hardware design of openwifi
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Mutual labels: fpga, verilog