Lenet acceleratorA Lenet ASIC Accelerator targeting minimum number of cycles
Stars: ✭ 17 (-46.87%)
Mutual labels: accelerator, verilog
hdl-toolsFacilitates building open source tools for working with hardware description languages (HDLs)
Stars: ✭ 56 (+75%)
Mutual labels: verilog
FPGA ThreeLevelStorage【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
Stars: ✭ 86 (+168.75%)
Mutual labels: verilog
drec-fpga-introMaterials for "Introduction to FPGA and Verilog" at MIPT DREC
Stars: ✭ 66 (+106.25%)
Mutual labels: verilog
speedy-antlr-toolGenerate an accelerator extension that makes your Antlr parser in Python super-fast!
Stars: ✭ 22 (-31.25%)
Mutual labels: accelerator
cnn openA hardware implementation of CNN, written by Verilog and synthesized on FPGA
Stars: ✭ 157 (+390.63%)
Mutual labels: verilog
svutSVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Stars: ✭ 48 (+50%)
Mutual labels: verilog
Solutions-to-HDLbits-Verilog-setsHere are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).
Stars: ✭ 57 (+78.13%)
Mutual labels: verilog
PyChip-py-hclA Hardware Construct Language
Stars: ✭ 36 (+12.5%)
Mutual labels: verilog
verilog-vcd-parserA parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
Stars: ✭ 46 (+43.75%)
Mutual labels: verilog
ics-adpcmProgrammable multichannel ADPCM decoder for FPGA
Stars: ✭ 18 (-43.75%)
Mutual labels: verilog
F9-Corner-Detection-LibraryA faster re-implementation of the FAST-9 algorithm (C++, with C bindings available)
Stars: ✭ 14 (-56.25%)
Mutual labels: corner-detection
gateware-tsHardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
Stars: ✭ 83 (+159.38%)
Mutual labels: verilog
yafpgatetrisYet Another Tetris on FPGA Implementation
Stars: ✭ 29 (-9.37%)
Mutual labels: verilog
virtioVirtio implementation in SystemVerilog
Stars: ✭ 38 (+18.75%)
Mutual labels: verilog
AtalantaAtalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
Stars: ✭ 49 (+53.13%)
Mutual labels: verilog
yahdlA programming language for FPGAs.
Stars: ✭ 20 (-37.5%)
Mutual labels: verilog
platform-lattice ice40Lattice iCE40: development platform for PlatformIO
Stars: ✭ 34 (+6.25%)
Mutual labels: verilog
sphinxcontrib-hdl-diagramsSphinx Extension which generates various types of diagrams from Verilog code.
Stars: ✭ 37 (+15.63%)
Mutual labels: verilog
spu32Small Processing Unit 32: A compact RV32I CPU written in Verilog
Stars: ✭ 51 (+59.38%)
Mutual labels: verilog
