All Projects → FAST9-Accelerator → Similar Projects or Alternatives

374 Open source projects that are alternatives of or similar to FAST9-Accelerator

Lenet accelerator
A Lenet ASIC Accelerator targeting minimum number of cycles
Stars: ✭ 17 (-46.87%)
Mutual labels:  accelerator, verilog
TinyGarble
TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits
Stars: ✭ 108 (+237.5%)
Mutual labels:  verilog
Trickster
Open Source HTTP Reverse Proxy Cache and Time Series Dashboard Accelerator
Stars: ✭ 1,306 (+3981.25%)
Mutual labels:  accelerator
Qkeras
QKeras: a quantization deep learning library for Tensorflow Keras
Stars: ✭ 254 (+693.75%)
Mutual labels:  accelerator
Saldl
A lightweight well-featured CLI downloader optimized for speed and early preview.
Stars: ✭ 203 (+534.38%)
Mutual labels:  accelerator
FPGA ThreeLevelStorage
【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。
Stars: ✭ 86 (+168.75%)
Mutual labels:  verilog
Snatch
A simple, fast and interruptable download accelerator, written in Rust
Stars: ✭ 623 (+1846.88%)
Mutual labels:  accelerator
drec-fpga-intro
Materials for "Introduction to FPGA and Verilog" at MIPT DREC
Stars: ✭ 66 (+106.25%)
Mutual labels:  verilog
picorv32 Xilinx
A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
Stars: ✭ 49 (+53.13%)
Mutual labels:  verilog
T13x
An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
Stars: ✭ 28 (-12.5%)
Mutual labels:  accelerator
Riverbed-Community-Toolkit
Riverbed Community Toolkit is a public toolkit for Riverbed Solutions engineering and integration
Stars: ✭ 16 (-50%)
Mutual labels:  accelerator
Download
Lantern官方版本下载 蓝灯 翻墙 代理 科学上网 外网 加速器 梯子 路由 proxy vpn circumvention gfw
Stars: ✭ 15,655 (+48821.88%)
Mutual labels:  accelerator
speedy-antlr-tool
Generate an accelerator extension that makes your Antlr parser in Python super-fast!
Stars: ✭ 22 (-31.25%)
Mutual labels:  accelerator
Lenet5 hls
FPGA Accelerator for CNN using Vivado HLS
Stars: ✭ 167 (+421.88%)
Mutual labels:  accelerator
cnn open
A hardware implementation of CNN, written by Verilog and synthesized on FPGA
Stars: ✭ 157 (+390.63%)
Mutual labels:  verilog
Lantern
Lantern官方版本下载 蓝灯 翻墙 代理 科学上网 外网 加速器 梯子 路由 lantern proxy vpn censorship-circumvention censorship gfw accelerator
Stars: ✭ 10,238 (+31893.75%)
Mutual labels:  accelerator
svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Stars: ✭ 48 (+50%)
Mutual labels:  verilog
Electron Localshortcut
Add keyboard shortcuts locally to a BrowserWindow instance, without using a Menu
Stars: ✭ 366 (+1043.75%)
Mutual labels:  accelerator
hdl-tools
Facilitates building open source tools for working with hardware description languages (HDLs)
Stars: ✭ 56 (+75%)
Mutual labels:  verilog
at
Accelerator Toolbox
Stars: ✭ 29 (-9.37%)
Mutual labels:  accelerator
tree-core-ide
The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
Stars: ✭ 79 (+146.88%)
Mutual labels:  verilog
Literatures-on-GNN-Acceleration
A reading list for deep graph learning acceleration.
Stars: ✭ 50 (+56.25%)
Mutual labels:  accelerator
ics-adpcm
Programmable multichannel ADPCM decoder for FPGA
Stars: ✭ 18 (-43.75%)
Mutual labels:  verilog
SpinalDev
Docker Development Environment for SpinalHDL
Stars: ✭ 17 (-46.87%)
Mutual labels:  verilog
tulingx
TULINGX(图灵)VPN下载页 翻墙 代理 科学上网 外网 加速器 梯子 路由
Stars: ✭ 59 (+84.38%)
Mutual labels:  accelerator
cobigen
Code-based Incremental Generator
Stars: ✭ 31 (-3.12%)
Mutual labels:  accelerator
COExperiment Repo
支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017
Stars: ✭ 23 (-28.12%)
Mutual labels:  verilog
F9-Corner-Detection-Library
A faster re-implementation of the FAST-9 algorithm (C++, with C bindings available)
Stars: ✭ 14 (-56.25%)
Mutual labels:  corner-detection
Aws Secure Environment Accelerator
The AWS Secure Environment Accelerator is a tool designed to help deploy and operate secure multi-account, multi-region AWS environments on an ongoing basis. The power of the solution is the configuration file which enables the completely automated deployment of customizable architectures within AWS without changing a single line of code.
Stars: ✭ 203 (+534.38%)
Mutual labels:  accelerator
gateware-ts
Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
Stars: ✭ 83 (+159.38%)
Mutual labels:  verilog
Kcptun
A Stable & Secure Tunnel based on KCP with N:M multiplexing and FEC. Available for ARM, MIPS, 386 and AMD64。KCPプロトコルに基づく安全なトンネル。KCP 프로토콜을 기반으로 하는 보안 터널입니다。
Stars: ✭ 12,714 (+39631.25%)
Mutual labels:  accelerator
yafpgatetris
Yet Another Tetris on FPGA Implementation
Stars: ✭ 29 (-9.37%)
Mutual labels:  verilog
Zou
A simple and fast download accelerator, written in Rust
Stars: ✭ 145 (+353.13%)
Mutual labels:  accelerator
virtio
Virtio implementation in SystemVerilog
Stars: ✭ 38 (+18.75%)
Mutual labels:  verilog
Oneapi Spec
oneAPI Specification source files
Stars: ✭ 75 (+134.38%)
Mutual labels:  accelerator
Atalanta
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
Stars: ✭ 49 (+53.13%)
Mutual labels:  verilog
power-gzip
POWER9 gzip engine documentation and code samples
Stars: ✭ 16 (-50%)
Mutual labels:  accelerator
platform-lattice ice40
Lattice iCE40: development platform for PlatformIO
Stars: ✭ 34 (+6.25%)
Mutual labels:  verilog
Jx
Jenkins X provides automated CI+CD for Kubernetes with Preview Environments on Pull Requests using Cloud Native pipelines from Tekton
Stars: ✭ 4,041 (+12528.13%)
Mutual labels:  accelerator
vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Stars: ✭ 325 (+915.63%)
Mutual labels:  verilog
Aparapi
The New Official Aparapi: a framework for executing native Java and Scala code on the GPU.
Stars: ✭ 352 (+1000%)
Mutual labels:  accelerator
Solutions-to-HDLbits-Verilog-sets
Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).
Stars: ✭ 57 (+78.13%)
Mutual labels:  verilog
Kcp
⚡ KCP - A Fast and Reliable ARQ Protocol
Stars: ✭ 10,473 (+32628.13%)
Mutual labels:  accelerator
vga-clock
Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Stars: ✭ 48 (+50%)
Mutual labels:  verilog
ILAng
A Modeling and Verification Platform for SoCs using ILAs
Stars: ✭ 52 (+62.5%)
Mutual labels:  accelerator
verilog-vcd-parser
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
Stars: ✭ 46 (+43.75%)
Mutual labels:  verilog
gemmini
Berkeley's Spatial Array Generator
Stars: ✭ 290 (+806.25%)
Mutual labels:  accelerator
kianRiscV
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
Stars: ✭ 167 (+421.88%)
Mutual labels:  verilog
e-verest
EVEREST: e-Versatile Research Stick for peoples
Stars: ✭ 21 (-34.37%)
Mutual labels:  accelerator
PyChip-py-hcl
A Hardware Construct Language
Stars: ✭ 36 (+12.5%)
Mutual labels:  verilog
CounterView
一个数字变化效果的计数器视图控件
Stars: ✭ 38 (+18.75%)
Mutual labels:  accelerator
my hdmi device
New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!
Stars: ✭ 66 (+106.25%)
Mutual labels:  verilog
trickster
Open Source HTTP Reverse Proxy Cache and Time Series Dashboard Accelerator
Stars: ✭ 1,753 (+5378.13%)
Mutual labels:  accelerator
yahdl
A programming language for FPGAs.
Stars: ✭ 20 (-37.5%)
Mutual labels:  verilog
fpga-docker
Tools for running FPGA vendor toolchains with Docker
Stars: ✭ 54 (+68.75%)
Mutual labels:  verilog
sphinxcontrib-hdl-diagrams
Sphinx Extension which generates various types of diagrams from Verilog code.
Stars: ✭ 37 (+15.63%)
Mutual labels:  verilog
spu32
Small Processing Unit 32: A compact RV32I CPU written in Verilog
Stars: ✭ 51 (+59.38%)
Mutual labels:  verilog
OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Stars: ✭ 124 (+287.5%)
Mutual labels:  verilog
xeda
Cross EDA Abstraction and Automation
Stars: ✭ 25 (-21.87%)
Mutual labels:  verilog
dbgbus
A collection of debugging busses developed and presented at zipcpu.com
Stars: ✭ 24 (-25%)
Mutual labels:  verilog
1-60 of 374 similar projects