Lenet acceleratorA Lenet ASIC Accelerator targeting minimum number of cycles
Stars: ✭ 17 (-46.87%)
TinyGarbleTinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits
Stars: ✭ 108 (+237.5%)
TricksterOpen Source HTTP Reverse Proxy Cache and Time Series Dashboard Accelerator
Stars: ✭ 1,306 (+3981.25%)
QkerasQKeras: a quantization deep learning library for Tensorflow Keras
Stars: ✭ 254 (+693.75%)
SaldlA lightweight well-featured CLI downloader optimized for speed and early preview.
Stars: ✭ 203 (+534.38%)
FPGA ThreeLevelStorage【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。
Stars: ✭ 86 (+168.75%)
SnatchA simple, fast and interruptable download accelerator, written in Rust
Stars: ✭ 623 (+1846.88%)
drec-fpga-introMaterials for "Introduction to FPGA and Verilog" at MIPT DREC
Stars: ✭ 66 (+106.25%)
picorv32 XilinxA picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
Stars: ✭ 49 (+53.13%)
T13xAn Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
Stars: ✭ 28 (-12.5%)
Riverbed-Community-ToolkitRiverbed Community Toolkit is a public toolkit for Riverbed Solutions engineering and integration
Stars: ✭ 16 (-50%)
DownloadLantern官方版本下载 蓝灯 翻墙 代理 科学上网 外网 加速器 梯子 路由 proxy vpn circumvention gfw
Stars: ✭ 15,655 (+48821.88%)
speedy-antlr-toolGenerate an accelerator extension that makes your Antlr parser in Python super-fast!
Stars: ✭ 22 (-31.25%)
Lenet5 hlsFPGA Accelerator for CNN using Vivado HLS
Stars: ✭ 167 (+421.88%)
cnn openA hardware implementation of CNN, written by Verilog and synthesized on FPGA
Stars: ✭ 157 (+390.63%)
LanternLantern官方版本下载 蓝灯 翻墙 代理 科学上网 外网 加速器 梯子 路由 lantern proxy vpn censorship-circumvention censorship gfw accelerator
Stars: ✭ 10,238 (+31893.75%)
svutSVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Stars: ✭ 48 (+50%)
Electron LocalshortcutAdd keyboard shortcuts locally to a BrowserWindow instance, without using a Menu
Stars: ✭ 366 (+1043.75%)
hdl-toolsFacilitates building open source tools for working with hardware description languages (HDLs)
Stars: ✭ 56 (+75%)
atAccelerator Toolbox
Stars: ✭ 29 (-9.37%)
tree-core-ideThe next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
Stars: ✭ 79 (+146.88%)
ics-adpcmProgrammable multichannel ADPCM decoder for FPGA
Stars: ✭ 18 (-43.75%)
SpinalDevDocker Development Environment for SpinalHDL
Stars: ✭ 17 (-46.87%)
tulingxTULINGX(图灵)VPN下载页 翻墙 代理 科学上网 外网 加速器 梯子 路由
Stars: ✭ 59 (+84.38%)
cobigenCode-based Incremental Generator
Stars: ✭ 31 (-3.12%)
COExperiment Repo支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017
Stars: ✭ 23 (-28.12%)
Aws Secure Environment AcceleratorThe AWS Secure Environment Accelerator is a tool designed to help deploy and operate secure multi-account, multi-region AWS environments on an ongoing basis. The power of the solution is the configuration file which enables the completely automated deployment of customizable architectures within AWS without changing a single line of code.
Stars: ✭ 203 (+534.38%)
gateware-tsHardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
Stars: ✭ 83 (+159.38%)
KcptunA Stable & Secure Tunnel based on KCP with N:M multiplexing and FEC. Available for ARM, MIPS, 386 and AMD64。KCPプロトコルに基づく安全なトンネル。KCP 프로토콜을 기반으로 하는 보안 터널입니다。
Stars: ✭ 12,714 (+39631.25%)
yafpgatetrisYet Another Tetris on FPGA Implementation
Stars: ✭ 29 (-9.37%)
ZouA simple and fast download accelerator, written in Rust
Stars: ✭ 145 (+353.13%)
virtioVirtio implementation in SystemVerilog
Stars: ✭ 38 (+18.75%)
Oneapi SpeconeAPI Specification source files
Stars: ✭ 75 (+134.38%)
AtalantaAtalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
Stars: ✭ 49 (+53.13%)
power-gzipPOWER9 gzip engine documentation and code samples
Stars: ✭ 16 (-50%)
JxJenkins X provides automated CI+CD for Kubernetes with Preview Environments on Pull Requests using Cloud Native pipelines from Tekton
Stars: ✭ 4,041 (+12528.13%)
vscode-terosHDLVHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Stars: ✭ 325 (+915.63%)
AparapiThe New Official Aparapi: a framework for executing native Java and Scala code on the GPU.
Stars: ✭ 352 (+1000%)
Kcp⚡ KCP - A Fast and Reliable ARQ Protocol
Stars: ✭ 10,473 (+32628.13%)
vga-clockShow the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Stars: ✭ 48 (+50%)
ILAngA Modeling and Verification Platform for SoCs using ILAs
Stars: ✭ 52 (+62.5%)
verilog-vcd-parserA parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
Stars: ✭ 46 (+43.75%)
gemminiBerkeley's Spatial Array Generator
Stars: ✭ 290 (+806.25%)
kianRiscVKianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
Stars: ✭ 167 (+421.88%)
e-verestEVEREST: e-Versatile Research Stick for peoples
Stars: ✭ 21 (-34.37%)
my hdmi deviceNew clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!
Stars: ✭ 66 (+106.25%)
tricksterOpen Source HTTP Reverse Proxy Cache and Time Series Dashboard Accelerator
Stars: ✭ 1,753 (+5378.13%)
yahdlA programming language for FPGAs.
Stars: ✭ 20 (-37.5%)
fpga-dockerTools for running FPGA vendor toolchains with Docker
Stars: ✭ 54 (+68.75%)
spu32Small Processing Unit 32: A compact RV32I CPU written in Verilog
Stars: ✭ 51 (+59.38%)
OpenROAD-flow-scriptsOpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Stars: ✭ 124 (+287.5%)
xedaCross EDA Abstraction and Automation
Stars: ✭ 25 (-21.87%)
dbgbusA collection of debugging busses developed and presented at zipcpu.com
Stars: ✭ 24 (-25%)