FPGA Cosmac ELF
This is a re-creation of a Cosmac ELF computer, Coded in SpinalHDL.
The goal of this project is to end up with a cycle-accurate 1802 processor that can be used in FPGA designs easily. When I start the project I was new to SpinalHDL but I had attempted in the past to write the same processor in VHDL. However, language complexity and the sheer amount of code and time needed to write and debug that project ended the work on it.
To make verification of the CPU easier, I made the simulation capable of reading the Emma debug trace log format.
The theory is that the CPU should follow that same path as the debug log from Emma.
If the Address or D register doesn't match the one in the log, then there is an issue and it will halt the simulation at that point.
Using GTKWave you can view the output of the simulation and debug the issue.
The test program included uses the Floating Point Subroutines by Paul Wasserman. I copied the subroutine listings by hand into a hex editor and checked them by overlaying an image of the hex code I copied, with the scanned images. Included is a copy of the scans, and a copy of the binary file for the subroutines. Along with the assemble code I wrote to test the CPU.
If you would like to learn more about the 1802 processor here's a video about the designer Joseph Weisbecker, For information about the Cosmac Elf computer there's the wiki page.
Way build an RCA1802 processor
Josh Bensadon had a goal when designing computers and that was they had to be fun.
The computer that led to the development of 1802 processor was called FRED.
The assembly language for the 1802 process is easy to understand, and the data flow of the cpu is easy to follow.
Using SpinalHDL made this project fun to work on.
The Verilog code generated by SpinalHDL for just the CPU is 1500 lines, and cpu1802.scala file is 700 lines.
I highly suggest installing and playing with SpinalHDL, it very powerful and the code is maintainable and reusable, and just works without the headaches.
Features:
- Able to load programs over the serial interface while in load mode. Bytes sent to the serial interface are loaded into ram using the DMA IN function.
- While in run and single step mode you can read the RX Serial data with INP N1 and check if it has data with BN2
- Interrupts are generated when the serial RX has data in its FIFO, and also when you press the write button. You can check the button state with BN4.
- Processor can send serial data with opcode OUT 1 and can check if the serial FIFO is full with opcode BN1
How to set up your project:
- You will need to have SpinalHDL setup and working on your system to generate the HDL code.
- For simulation, you will need to have Verilator setup.
- In your FPGA project, you will need to generate a PPL with a clock out of 8mhz to have the serial baud rate be 115200
- You will also need to generate a block ram.
- You may have to edit the BlackBoxes for the PLL and Ram to match your targets.
- or you can just generate the CPU core by itself to get the HDL/Verilog.
- or copy the cpu1802.scala file to your own SpinalHDL project.
