598 Open source projects that are alternatives of or similar to FPGACosmacELF

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

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A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

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KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

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shdl6800: A 6800 processor written in SpinalHDL

A reimplementation of a tiny stack CPU

SweRV EL2 Core

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Single header Z80 emulator for C++ (C++11 or later)

EVEREST: e-Versatile Research Stick for peoples

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

RISC-V processor emulator written in Rust+WASM

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

A MIPS CPU implemented in Verilog

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32-bit Superscalar RISC-V CPU

Simple, orthogonal 32-bit computer architecture and environment

🔬 dd's x86 CPU Identification tool

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

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FPGA-based RISC-V CPU+SoC.

Docker Development Environment for SpinalHDL

Processor Counter Monitor

SystemOT, yet another home brew cpu.

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

SweRV EH1 core

The OpenPiton Platform

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Clio, ASPLOS'22.

ROS 2 Hardware Acceleration Working Group community governance model & list of projects

The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

A 8-bit computer made of 74xx series logic gates and memory ICs.

A FPGA friendly 32 bit RISC-V CPU implementation

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

Managed Machine Learning Systems and Internet of Things Live Lesson

linux运维监控工具，支持系统信息，内存，cpu，温度，磁盘空间及IO，硬盘smart，系统负载，网络流量等监控，API接口，大屏展示，拓扑图，进程监控，端口监控，docker监控，文件防篡改，日志监控，数据可视化，web ssh，堡垒机，指令下发批量执行，linux面板，探针，故障告警

Collection of links to great software development resources!

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ROS wrapper for Kimera-VIO

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

Modern improvements for MIT's xv6 OS

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F# RISC-V Instruction Set formal specification

GPU/CPU-based iOS Watermark Library for Image and Video Overlay

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs