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BackdoorA backdoor that runs on Linux and Windows
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la-coreLinear algebra accelerators for RISC-V (published in ICCD 17)
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quasiSoCNo-MMU Linux capable RISC-V SoC designed to be useful.
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natsA program to hide file into executable binary.
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srv32Simple 3-stage pipeline RISC-V processor
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yarviYet Another RISC-V Implementation
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crypto🔐 Fastest crypto library for Deno written in pure Typescript. AES, Blowfish, CAST5, DES, 3DES, HMAC, HKDF, PBKDF2
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vega-liteSoftware, tools, and documentation for RV32-VEGA-Lite platform
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SpinalCryptoSpinalHDL - Cryptography libraries
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WebRISC-VWebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
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PassLockPassLock is a medium-security password manager that encrypts passwords using Advanced Encryption Standards (AES)
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nimsslNimssl is a Nim wrapper for the OpenSSL library
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tinyaes-pytiny-AES-c wrapper in Cython
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galoisA performant NumPy extension for Galois fields and their applications
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Qt-SecretSimple encryption library supporting RSA and AES algorithms.
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chat-diffie-hellmanA secure chat between an Android client and Java server using AES for encryption and Diffie-Hellman for key exchange.
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drec-fpga-introMaterials for "Introduction to FPGA and Verilog" at MIPT DREC
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stencSCSI Tape Encryption Manager - stenc (formerly on https://sourceforge.net/projects/stenc/)
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cryptocliThe ultimate tool for data transfer, manipulation and proxy.
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wx-ding-aesNode.js 微信开放平台、企业微信、钉钉第三方回调接口 AES 解密库
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sednaSedna - a pure Java RISC-V emulator.
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aes-rijndaelaes (rijndael) implementation
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derzforthBare-metal Forth implementation for RISC-V
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Reverse-EngineeringA FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit ARM & 64-bit ARM architectures.
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opensslA functions wrapping of OpenSSL library for symmetric and asymmetric encryption and decryption.
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yatcpuYet another toy CPU.
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bl mcu sdkbl_mcu_sdk is MCU software development kit provided by Bouffalo Lab Team for BL602/BL604, BL702/BL704/BL706, BL616/BL618, BL808 and other series of RISC-V based chips in the future.
Stars: ✭ 147 (+234.09%)
ravelA RISC-V simulator
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osmiumA toy operating system written in Rust on RISC V(rv32im)
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r3R3-OS — Experimental static (μITRON-esque) RTOS for deeply embedded systems, testing the limit of Rust's const eval and generics
Stars: ✭ 87 (+97.73%)
Python-SecureHTTPMake HTTP transmissions more secure via RSA+AES, encrypted communication for C/S architecture.
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riscv emSimple risc-v emulator, able to run linux, written in C.
Stars: ✭ 51 (+15.91%)
ARM9-compatible-soft-CPU-coreThis ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
Stars: ✭ 42 (-4.55%)
steel-coreProcessor core implementing the base RV32I instruction set of the RISC-V ISA
Stars: ✭ 67 (+52.27%)
fosInteresting project,the Fast Real Time Operating Systems( FOS-RTOS)
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spu32Small Processing Unit 32: A compact RV32I CPU written in Verilog
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rv32i-simRISC-V Software Simulation
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KyogenRVThe Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
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cryptopocket🔐 Encrypt anything, then Decrypt by providing a required key.
Stars: ✭ 22 (-50%)
nuclei-sdkNuclei RISC-V Software Development Kit
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OpenAdBlockThe free, open-source Content Blocker for 32- and 64-bit iOS devices
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epaterAn ARM emulator in Python for educational purposes
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webcryptoA WebCrypto Polyfill for NodeJS
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Xassette-AsteriskEvaluation board for AllWinner's RISC-V 64 SoC F133/D1s
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WMIC++ WMI class library
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etissExtendable Translating Instruction Set Simulator
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