117 Open source projects that are alternatives of or similar to Firechip

QEMU platform SBI support implementation, using RustSBI

Fast constant-time AES implementations on 32-bit architectures

A secure embedded operating system for microcontrollers

Let's write an OS which can run on RISC-V in Rust from scratch!

Yet Another RISC-V Implementation

A self-hosting and educational C compiler

MDEPX — A BSD-style RTOS

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Evaluation board for AllWinner's RISC-V 64 SoC F133/D1s

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

The RISC-V software tools list, as seen on riscv.org

R3-OS — Experimental static (μITRON-esque) RTOS for deeply embedded systems, testing the limit of Rust's const eval and generics

RISC-V Assembler and Runtime Simulator

hub.docker.com/repository/docker/davidburela/riscv-emulator

RISC-V Cores, SoC platforms and SoCs

Multi-Platform C code Library for EVE graphics controllers from FTDI / Bridgetek (FT810, FT811, FT812, FT813, BT815, BT816, BT817, BT818)

RISC-V CPU Core (RV32IM)

This tutorial provides one example on how a CI (Continuous Integration) workflow with the IAR Build Tools for Linux can be set up on GitHub. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

A graphical processor simulator and assembly editor for the RISC-V ISA

Simple risc-v emulator, able to run linux, written in C.

Nuclei Microcontroller Software Interface Standard Development Repo

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

RARS -- RISC-V Assembler and Runtime Simulator

Software, tools, and documentation for RV32-VEGA-Lite platform

A RISC-V 32bit single-cycle CPU written in Logisim

⛔ DEPRECATED ⛔ HERO Software Development Kit

RISC-V Software Simulation

The RISC-V software tools list, as seen on riscv.org

List of ideas for getting started with TimVideos projects

The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (formerly known as the GNU MCU Eclipse plug-ins). Includes the archive of previous plug-ins versions, as Releases.

Riscv32 CPU Project

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

RT-Thread is an open source IoT operating system.

Lightweight and performant dynamic binary translation for RISC–V code on x86–64

OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32

ARV: Asynchronous RISC-V Go High-level Functional Model

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

RISC-V RV32I[MAC] emulator with ELF support

Maxine VM: A meta-circular research VM

BL602 SDK (Pine64 fork)

Alphanumeric+1 shellcoding tools for RISC-V

Kendryte K210 BSP for RT-Thread

RISC-V processor emulator written in Rust+WASM

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

Sedna - a pure Java RISC-V emulator.

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

A RISC-V simulator

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Interesting project，the Fast Real Time Operating Systems( FOS-RTOS)

A simple three-stage RISC-V CPU

Yet another toy CPU.

SweRV EH1 core

Homebrew game for homebrew FPGA game console

Featherweight RISC-V implementation

Reko is a binary decompiler.

Renode - Antmicro's virtual development framework for complex embedded systems

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

A 32-bit RISC-V emulator in a shader (and C)