Basic verilogMust-have verilog systemverilog modules
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Project ZiplineDefines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.
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Fpga Litecoin MinerA litecoin scrypt miner implemented with FPGA on-chip memory.
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SpispyAn open source SPI flash emulator and monitor
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ZetOpen source implementation of a x86 processor
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Fpusynthesiseable ieee 754 floating point library in verilog
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OpentimerA High-performance Timing Analysis Tool for VLSI Systems
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FluteRISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
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LitepcieSmall footprint and configurable PCIe core
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Biriscv32-bit Superscalar RISC-V CPU
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Red Pitaya NotesNotes on the Red Pitaya Open Source Instrument
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Verilog 6502A Verilog HDL model of the MOS 6502 CPU
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Fpga nesFPGA-based Nintendo Entertainment System Emulator
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PiccoloRISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
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RidecoreRIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
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Basejump stlBaseJump STL: A Standard Template Library for SystemVerilog
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Openwifi HwFPGA/hardware design of openwifi
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Wb2axipBus bridges and other odds and ends
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FpgaThe USRP™ Hardware Driver FPGA Repository
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AccdnnA compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
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Tinyfpga B SeriesOpen source design files for the TinyFPGA B-Series boards.
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KestrelThe Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.
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Verilog I2cVerilog I2C interface for FPGA implementation
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PoprcA Compiler for the Popr Language
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Sv ParserSystemVerilog parser library fully complient with IEEE 1800-2017
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Fpga Chip8CHIP-8 console on FPGA
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MetroboyMetroBoy - A playable, circuit-level simulation of an entire Game Boy
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KryonFPGA,Verilog,Python
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Cnn Fpga使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用
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Sha256Hardware implementation of the SHA-256 cryptographic hash function
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Fpg1PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.
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DegateOpen source software for chip reverse engineering.
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TinytpuImplementation of a Tensor Processing Unit for embedded systems and the IoT.
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Sv2vSystemVerilog to Verilog conversion
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Learning Nvdla NotesNVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]
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LogicCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
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