342 Open source projects that are alternatives of or similar to Scale Mamba

浙江大学计算机体系结构课程实验

GPGPU microprocessor architecture

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LicheeTang 蜂鸟E203 Core

Ham Radio hat for Raspberry PI

i8080 precise replica in Verilog, based on reverse engineering of real die

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

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Dreamcast HDMI

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

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open-source IEEE 802.11 WiFi baseband FPGA (chip) design

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FuseSoC-based SoC for SweRV EH1

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

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Silicon-validated SoC implementation of the PicoSoc/PicoRV32

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Bitcoin miner for Xilinx FPGAs

All code found on nandland is here. underconstruction.gif

RePlAce global placement tool

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A convolutional neural network implemented in hardware (verilog)

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Repurposing existing HDL tools to help writing better code

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Verilog module for calculation of FFT.

A Verilog implementation of DisplayPort protocol for FPGAs

A List of Free and Open Source Hardware Verification Tools and Frameworks

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

A 32-bit Microcontroller featuring a RISC-V core

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Pano Logic G2 Reverse Engineering Project

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

Light-weight RISC-V RV32IMC microcontroller core.

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奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

A simple, basic, formally verified UART controller

Compact FPGA game console

Verilog version of Z-scale (deprecated)

FPGA implementation of Cellular Neural Network (CNN)

iCESugar FPGA Board (base on iCE40UP5k)

Regression test suite for Icarus Verilog.

Core description files for FuseSoC

A nicer HDL.

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Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilog compiler and language services

Chisel 3: A Modern Hardware Design Language

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FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

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