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3 open source projects by dpretet

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Repository gathering basic modules for CDC purpose

✭ 30

SystemVerilog Verilog forth asic timing fifo cdc fgpa cross-domain-crossing pulse-synchronizer

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

✭ 117

Verilog SystemVerilog fpga verification verilog synthesis icarus-verilog fifo hdl verilog-hdl fifo-queue fifo-cache

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

✭ 48

python SystemVerilog shell Verilog C++simulator tdd simulation foss verilog testcase tdd-utilities mit-license icarus-verilog gtkwave verification-methodologies vcd verilator svut

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