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All Projects → peteut → migen-axi

peteut / migen-axi

Licence: MIT license
AXI support for Migen/MiSoC

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python
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hdlmisocmigenzynq-7000

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Migen AXI

Build Status Coverage Status

This repo contains some Migen modules created to support some MiSoC features on the Xilinx Zynq SoC. A Zedboard is used for testing, the existing platform from Migen is used as baseline and extended as necessary.

Cores

  • wrapper for PS7

Interconnect

  • AXI2CSR
  • P2P interconnect
  • InterconnectShared
  • Crossbar
  • Writer, AXI3 Slave + CoreLink DMA-330 DMA Controller Peripheral Request Interface (PRI)

By now only P2P interconnect is in actual use, where M_AXI_GP0 is wired to a custom AXI3 slave and M_AXI_GP1 is wired to a AXI2CSR bridge.

Linux Support

  • Device-tree overlay generator for iomem, irqs, firmware

Device-tree overlay is supported by Linux, currently .dts is crafted manually but shall be automatically generated. Overlays with firmware loading has been tested on a 4.9 Linux. To allow for phandles DTS_FLAGS+='-@ -H epapr' may be used.

License

Released under the MIT license, see LICENSE file for info.

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].