pygearsHW Design: A Functional Approach
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LogicCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
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Mutual labels: asic, fpga, verilog
LivehdLive Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
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Mutual labels: asic, fpga, verilog
RiscvRISC-V CPU Core (RV32IM)
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Mutual labels: asic, fpga, verilog
virtioVirtio implementation in SystemVerilog
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Mutual labels: fpga, verilog, hdl
Clash CompilerHaskell to VHDL/Verilog/SystemVerilog compiler
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Mutual labels: asic, fpga, verilog
AesVerilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
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Mutual labels: asic, fpga, verilog
Open Register Design ToolTool to generate register RTL, models, and docs using SystemRDL or JSpec input
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Mutual labels: asic, fpga, verilog
gateware-tsHardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
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Mutual labels: fpga, verilog, hdl
xedaCross EDA Abstraction and Automation
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Mutual labels: fpga, verilog, hdl
CoresVarious HDL (Verilog) IP Cores
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Mutual labels: asic, fpga, verilog
async fifoA dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
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Mutual labels: fpga, verilog, hdl
Speech256An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
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Mutual labels: fpga, verilog, hdl
RggenCode generation tool for configuration and status registers
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Mutual labels: asic, fpga, verilog
Biriscv32-bit Superscalar RISC-V CPU
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Mutual labels: asic, fpga, verilog
sphinxcontrib-hdl-diagramsSphinx Extension which generates various types of diagrams from Verilog code.
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Mutual labels: fpga, verilog, hdl
DFiantDFiant: A Dataflow Hardware Descripition Language
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Mutual labels: asic, fpga, hdl
OpenLaneOpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
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Mutual labels: asic, verilog
dblclockfftA configurable C++ generator of pipelined Verilog FFT cores
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Mutual labels: fpga, verilog
FPGA-USB-DeviceFPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.
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Mutual labels: fpga, verilog