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virtioVirtio implementation in SystemVerilog
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JSON-for-VHDLA JSON library implemented in VHDL.
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vivado-dockerDockerfile with Vivado for CI
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intfftkFully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
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Openwifiopen-source IEEE 802.11 WiFi baseband FPGA (chip) design
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eddr3mirror of https://git.elphel.com/Elphel/eddr3
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Deep-DarkFantasyGlobal Dark Mode for ALL apps on ANY platforms.
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ixo-usb-jtagusb-jtag - Altera USB Blaster Emulation with a FX2
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SHA256HasherSHA-256 IP core for ZedBoard (Zynq SoC)
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SDR Matlab LTE📡 Using Software Designed Radio to transmit LTE downlink signals at 2.4 GHz
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awesome-hwd-toolsA curated list of awesome open source hardware design tools
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polyphonyPolyphony is Python based High-Level Synthesis compiler.
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