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All Projects → TM90 → awesome-hwd-tools

TM90 / awesome-hwd-tools

Licence: GPL-3.0 license
A curated list of awesome open source hardware design tools

Labels

asicfpgahardwareawesome-listdesign-automation

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awesome-hwd-tools

A curated list of awesome open source hardware design tools with a focus on chip design.

For electronic hardware tools without a focus on chip design see:

https://github.com/kitspace/awesome-electronics

Inspired by awesome-python.

Semi Custom Design/ FPGAs

Nic30/hdlConverter - Python System-Verilog/VHDL Parser

christiklein/simpy - discrite event based simulation framework

chipmuenk/pyFDA - A python tool to design time discrete filters

efabless/openlane - Automated RTL to GDS flow based on openRoad, Yosys and more...

ahmed-agiza/EDAViewer - EDAV is a cloud-based open-source viewer for electronic design automation (EDA) design files (LEF, DEF)

Modelling

cornell-brg/pymtl3 - hardware modeling framework

mortbopet/VSRTL - Visual Simulation of Register Transfer Logic

Hardware Description Languages

freechipsproject/Chisel - Hardware Description Language embedded in Scala developed at UC Berkeley

phanrahan/Magma - A Hardware Description Language embedded in Python

freechipsproject/firrtl - Intermediate representation for rtl (used by Chisel and Magma)

myhdl/MyHDL - Python as a Hardware Description and Verification Language

clash-lang/clash-compiler - A Hardware Description Language written and inspired by Haskell

A much more detailed and specific list for hardware description languages can be found at drom/awesome-hdl.

Wave Viewers

gtkwave - GTK based waveform viewer

wavedrom/wavedrom - Timing Diagrams in Java Script

Simulation

steveicarus/iverilog - Icarus Verilog Simulator

ghdl/ghdl - VHDL Simulator

Synthesis

YosysHQ/yosys - Synthesis Flow

Timing Analysis

abk-openroad/OpenSTA - static timing analysis

OpenTimer/OpenTimer - timing analysis tool for vlsi systems

Verification

YosysHQ/SymbiYosys - formal verification flow and tool

cocotb/cocotb - Creating Verilog/VHDL testbenches with python

Open Source PDK

leviathanch/libresiliconprocess - A 1um open process specification

google/skywater-pdk - Open Source Process SkyWater 130nm

Full Custom Design

heitzmann/gdspy - manipulating GDSII files in Python

unihd-cag/skillbridge - A seamless python to Cadence Virtuoso Skill interface

rbzentrum/SPAM - SPAM is a package management system for Cadence SKILL

rbzentrum/ml2tikz - Virtuoso layout to tikzpicture

MatthewLoveQUB/SKILL_Tools - Skill++ Tools including a test framework

EDDRSoftware/oaFileParser - oaFile Parser

scikit-rf/scikit-rf - RF and Microwave Design in scikit

mph-/lcapy - Lcapy is a Python package for linear circuit analysis. It uses SymPy for symbolic mathematics.

YosysHQ/PADRING - A padring generator for asics

DegateCommunity/Degate - Tool for VLSI reverse engineering

Layout Generation/ Manipulation

ucb-art/BAG_framework - Berkeley Analog Generator

VLSIDA/OpenRAM - open-source SRAM Compiler

KLayout/klayout - scriptable Layout Viewer and Editor

Simulation

ngspice - Spice Simulator

FabriceSalvaire/pyspice - Simulating and creating Spice Circuits with Python

Mixed Signal Design

Isotel/mixedsim - A mixed signal simulation approach using ngspice and yosys providing a library mapping to spice

Documentation

SchemDraw - producing circuit diagrams with python

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