Top 22 xilinx open source projects

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

✭ 2,257

c shell python linux verilog wifi fpga hls sdr software-defined-radio zynq xilinx analog-devices ieee80211 xilinx-fpga dma ofdm csma ad9361 802-11 mac80211 openwifi

ixo-usb-jtag

usb-jtag - Altera USB Blaster Emulation with a FX2

✭ 49

C++c assembly Makefile fpga xilinx altera usb-devices openocd jtag numato-opsis digilent-atlys cypress-fx2 ezusb digilent opsis numato urjtag

Xilinx-ISE-Makefile

An example of how to use the Xilinx ISE toolchain from the command line

✭ 50

Makefile fpga xilinx xilinx-ise

PYNQ Composable Pipeline

PYNQ Composabe Overlays

✭ 25

tcl Jupyter Notebook python Verilog C++Makefile fpga xilinx pynq composable

intfftk

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

✭ 43

VHDL Verilog matlab fpga dsp vhdl verilog fast-fourier-transform xilinx fft vivado altera cooley-tukey-fft digital-signal-processing fast-convolutions radix-2 integer-arithmetic route-optimization

Deep-DarkFantasy

Global Dark Mode for ALL apps on ANY platforms.

✭ 16

Verilog tcl SystemVerilog Makefile shell javascript fpga zynq dark-theme verilog xilinx vivado verilog-hdl dark-mode zynq-7000 dark-mode-toggle

prjxray-db

Project X-Ray Database: XC7 Series

✭ 52

shell Makefile toolchain bitset database tools fpga xilinx xilinx-fpga artix7 artix kintex7 symbiflow prjxray

JSON-for-VHDL

A JSON library implemented in VHDL.

✭ 56

VHDL TeX powershell Batchfile parser json fpga simulation vhdl xilinx synthesis lattice fileformat modelsim questasim ghdl

eddr3

mirror of https://git.elphel.com/Elphel/eddr3

✭ 33

Verilog SystemVerilog python HCL fpga zynq ddr verilog xilinx open-core ddr3 memory-controller

SDR Matlab OFDM 802.11n

📡 Using Software Designed Radio to transmit MIMO-OFDM QPSK signals at 5 GHz

✭ 44

matlab radio gui zynq hardware xilinx sdr analog-devices zedboard ieee80211 ofdm qpsk preamble ad9361 fmcomms3 fmcomms 80211 mimo xilinx-zynq transmit-ofdm-signals

EBAZ4205

Vivado and PetaLinux projects for Zynq EBAZ4205 Board

✭ 38

HTML c tcl fpga zynq xilinx vivado petalinux ebaz4205

vim-hdl

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

✭ 59

python Vim Script shell Dockerfile productivity vhdl vim-plugins verilog xilinx syntastic syntax-checker altera modelsim

PothosZynq

DMA source and sink blocks for Xilinx Zynq FPGAs

✭ 19

VHDL HTML Coq c Verilog tcl fpga zynq xilinx vivado dma pothos pothos-framework

ResNet50-PYNQ

Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ

✭ 42

C++c xilinx pynq alveo finn

vivado-docker

Dockerfile with Vivado for CI

✭ 22

docker fpga xilinx vivado

virtio

Virtio implementation in SystemVerilog

✭ 38

SystemVerilog CMake python Vim Script cmake fpga model rtl verilog xilinx vivado systemc hdl virtio verilator quartus

zc pcie dma

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

✭ 37

tcl Verilog c python CartoCSS Makefile linux kernel fpga zynq xilinx dma axi-dma pci-e

xup compute acceleration

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

✭ 41

C++Jupyter Notebook fpga xilinx vitis xup

SHA256Hasher

SHA-256 IP core for ZedBoard (Zynq SoC)

✭ 25

Verilog SystemVerilog tcl c arm fpga zynq xilinx sha256 vivado soc zedboard

ezdma

Simple, zero-copy DMA to/from userspace.

✭ 70

c Makefile linux zynq xilinx dma xilinx-axi-dma

SDR Matlab LTE

📡 Using Software Designed Radio to transmit LTE downlink signals at 2.4 GHz

✭ 21

matlab c radio gui zynq hardware xilinx sdr iio analog-devices zedboard software-defined-radio ofdm ad9361 fmcomms3 fmcomms xilinx-zynq 64qam

fpga-docker

Tools for running FPGA vendor toolchains with Docker

✭ 54

Makefile Dockerfile shell fpga vhdl verilog xilinx altera lattice quartus

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